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1.发明授权Local objective optimization in global placement of an integrated circuit design 失效集成电路设计的全局放置中的局部目标优化公开(公告)号：US08595675B1
公开(公告)日：2013-11-26
申请号：US13539428
申请日：2012-06-30
CPC分类号： G06F17/5072
摘要： A global placement phase of physical design of an integrated circuit includes iteratively spreading a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and optimizing module placement by preserving global module density while improving a local objective, such as local wirelength and/or local density, in individual subareas among a plurality of subareas of the die area. After global placement, detailed placement of modules in the plurality of subareas is performed.
摘要翻译： 集成电路的物理设计的全局放置阶段包括基于多个模块的密度迭代地扩展包含该集成电路的多个模块，并且通过保持全局模块密度来优化模块放置，同时改善本地目标，例如 作为模具区域的多个子区域中的各个子区域中的局部线长度和/或局部密度。 在全局放置之后，执行在多个子区域中的模块的详细放置。
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2.发明申请MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN 失效集成电路设计中的多图形图形识别芯片布局公开(公告)号：US20130086543A1
公开(公告)日：2013-04-04
申请号：US13248711
申请日：2011-09-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。 执行细胞运动的全局阶段。 执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位 在为IC设计制作最终布局之前。
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公开(公告)号：US08347249B2
公开(公告)日：2013-01-01
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F9/455
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译： 公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。 电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。 每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。 第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。 响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少 关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。 响应于合法化，EDA系统递增地优化多个路径的时间延迟。
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4.发明申请公开(公告)号：US20120284733A1
公开(公告)日：2012-11-08
申请号：US13550957
申请日：2012-07-17
申请人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
发明人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
IPC分类号： G06F9/46
CPC分类号： G06F17/50 , G06F9/5066
摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.
摘要翻译： 区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。 对于少量的移动端口，通过平衡可放置对象来分配计算。 对于每次移动的少量对象，通过平衡移动端口分配计算。 如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。 对于对象平衡，移动端口被分配给一个处理器，直到处理器的摊销对象数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。 对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。 本发明提供多项式时间的时间表，同时保持高质量的结果。
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公开(公告)号：US07467369B2
公开(公告)日：2008-12-16
申请号：US11554235
申请日：2006-10-30
CPC分类号： G06F17/5072
摘要： The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.
摘要翻译： 说明性实施例提供了一种计算机实现的方法，其执行减小总线长度的小区变换，而不降低设备定时或违反电气约束。 该过程计算数据集的延迟约束系数。 该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。 该过程计算用于变换数据集合的加权总线长度递增值。 此外，该过程通过评估抵达时间约束，电气约束和用户可配置的违规移动限制，以及如果发现违规，则将移动单元恢复到原始位置继续。
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6.发明申请METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 有权通过扩展力矢量调制降低分析放置技术的线性的方法公开(公告)号：US20080282213A1
公开(公告)日：2008-11-13
申请号：US12181447
申请日：2008-07-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
摘要翻译： 提出了一种强制定向布置程序的方法。 该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。
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7.发明授权公开(公告)号：US07399926B2
公开(公告)日：2008-07-15
申请号：US11490990
申请日：2006-07-20
申请人： Chan-Yong Park , Gi-Joon Nam , Jong-Seb Baeck , Woo-Yong Dong
发明人： Chan-Yong Park , Gi-Joon Nam , Jong-Seb Baeck , Woo-Yong Dong
IPC分类号： H01B11/02
CPC分类号： H01B11/06
摘要： A communication cable includes at least one twisted wire pair formed by twisting a plurality of insulation-coated wires; a sheath surrounding the twisted wire pair; and a protrusion formed on an outer surface of the sheath. This communication cable may prevent alien crosstalk particularly at high-speed transmission so that transmission characteristics of the communication cable may be stably kept.
摘要翻译： 通信电缆包括通过扭绞多个绝缘被覆线而形成的至少一根双绞线; 围绕双绞线对的护套; 以及形成在护套的外表面上的突起。 该通信电缆可以防止异常串扰，特别是在高速传输时，可以稳定地保持通信电缆的传输特性。
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公开(公告)号：US20080127017A1
公开(公告)日：2008-05-29
申请号：US11554235
申请日：2006-10-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method and a computer program product which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. The process computes a weighted total wire length incremented value for the transformed data set, if the move will not improve placement, the move transform is not allowed. Further, the process continues by evaluating arrival time constraints, electrical constraints and user configurable move limits for violations, restoring the move cells to the original placement if a violation is found.
摘要翻译： 一种计算机实现的方法和一种计算机程序产品，其执行减少总线长度的小区变换，而不会降低设备定时或违反电气限制。 该过程计算数据集的延迟约束系数。 该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。 该过程计算变换数据集的加权总线长度递增值，如果移动不会改善放置，则不允许移动变换。 此外，该过程通过评估到达时间约束，电气约束和用户可配置的违规移动限制来继续，如果发现违规，则将移动单元恢复到原始位置。
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公开(公告)号：US07221833B2
公开(公告)日：2007-05-22
申请号：US10979586
申请日：2004-11-02
申请人： Do-Hyun Park , Gi-Joon Nam
发明人： Do-Hyun Park , Gi-Joon Nam
IPC分类号： G02B6/44
CPC分类号： G02B6/4401 , G02B6/4495
摘要： Disclosed is an optical cable with a secondary sheath for surrounding and protecting a plurality of optical fiber units in which at least 1-core optical fiber is mounted in a buffer tube, wherein the secondary sheath is made of a mixture including 100 parts by weight of base resin selected from the group consisting of low density polyethylene, linear low density polyethylene, and their mixture; and 0.2 to 60 parts by weight of inorganic additive. The secondary sheath of this optical cable shows excellent cutting and tear characteristics and ensures easy contact and divergence.
摘要翻译： 公开了一种具有次级护套的光缆，用于围绕和保护多个光纤单元，其中至少1芯光纤安装在缓冲管中，其中，第二护套由包含100重量份的 选自低密度聚乙烯，线性低密度聚乙烯及其混合物的基础树脂; 和0.2〜60重量份的无机添加剂。 该光缆的次级护套显示出优异的切割和撕裂特性，并确保容易接触和发散。
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公开(公告)号：US20070044995A1
公开(公告)日：2007-03-01
申请号：US11513296
申请日：2006-08-29
申请人： Chan-Yong Park , Jong-Seb Baeck , Gi-Joon Nam , Woo-Yong Dong
发明人： Chan-Yong Park , Jong-Seb Baeck , Gi-Joon Nam , Woo-Yong Dong
IPC分类号： H01B7/00
CPC分类号： H01B11/06
摘要： A separator for a communication cable includes a plurality of barriers formed in a radial direction so that at least two pair units, in each of which at least two insulation-coated wires are spirally twisted, are received in spaces formed by the barriers one by one so as to separate the pair units from each other. At least one of the barriers has a relatively greater thickness than the other barriers. Thus, a communication cable having the separator may prevent PSNEXT (Power Sum Near and Crosstalk) caused by interference between adjacent wires when a high frequency signal is transmitted through the wires.
摘要翻译： 用于通信电缆的隔板包括在径向方向上形成的多个屏障，使得至少两个绝缘涂覆的电线螺旋地扭曲的至少两对单元被一个接一个地由屏障形成的空间中接收 以便将对单元彼此分离。 至少一个障碍物的厚度比其他障碍物具有相对较大的厚度。 因此，具有分离器的通信电缆可以防止当高频信号通过电线传输时由相邻电线之间的干扰引起的PSNEXT（功率和近似和串扰）。
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