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US07470591B2 Method of forming a gate stack containing a gate dielectric layer having reduced metal content 失效
形成包含具有降低的金属含量的栅极电介质层的栅极堆叠的方法

Method of forming a gate stack containing a gate dielectric layer having reduced metal content
摘要：
A method is provided for reducing the metal content and controlling the metal depth profile of a gate dielectric layer in a gate stack. The method includes providing a substrate in a process chamber, depositing a gate dielectric layer on the substrate, where the gate dielectric layer includes a metal element. The metal element is selectively etched from at least a portion of the gate dielectric layer to form an etched gate dielectric layer with reduced metal content, and a gate electrode layer is formed on the etched gate dielectric layer.
摘要（中）：

提供了一种用于降低金属含量并控制栅叠层中的栅介质层的金属深度分布的方法。 该方法包括在处理室中提供衬底，在衬底上沉积栅极电介质层，其中栅极电介质层包括金属元素。 从栅介质层的至少一部分选择性地蚀刻金属元件，以形成具有降低的金属含量的蚀刻栅极电介质层，并且在蚀刻的栅极介电层上形成栅极电极层。

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