发明授权
US07479432B2 CMOS transistor junction regions formed by a CVD etching and deposition sequence
有权
通过CVD蚀刻和沉积顺序形成CMOS晶体管结区域
- 专利标题: CMOS transistor junction regions formed by a CVD etching and deposition sequence
- 专利标题(中): 通过CVD蚀刻和沉积顺序形成CMOS晶体管结区域
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申请号: US11643523申请日: 2006-12-21
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公开(公告)号: US07479432B2公开(公告)日: 2009-01-20
- 发明人: Anand Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Jeffrey R. Wank
- 申请人: Anand Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Jeffrey R. Wank
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: H01L27/108
- IPC分类号: H01L27/108
摘要:
This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
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