发明授权
- 专利标题: Measuring and predicting VLSI chip reliability and failure
- 专利标题(中): 测量和预测VLSI芯片的可靠性和故障
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申请号: US12049344申请日: 2008-03-16
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公开(公告)号: US07480882B1公开(公告)日: 2009-01-20
- 发明人: Peilin Song , David Heidel , Franco Motika , Franco Stellari
- 申请人: Peilin Song , David Heidel , Franco Motika , Franco Stellari
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: MaxValueIP, LLC
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F19/00 ; G06F11/27 ; G01R31/3187 ; G01R31/28
摘要:
This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.
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