Invention Grant
- Patent Title: Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource
- Patent Title (中): 使用另一个处理器资源处理处理器异构资源的地址转换和异常
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Application No.: US11477643Application Date: 2006-06-29
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Publication No.: US07487341B2Publication Date: 2009-02-03
- Inventor: Hong Wang , Hong Jiang , John Shen , Porus S. Khajotia , Ming W. Choy , Narayan Biswal
- Applicant: Hong Wang , Hong Jiang , John Shen , Porus S. Khajotia , Ming W. Choy , Narayan Biswal
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F9/00
- IPC: G06F9/00 ; G06F12/10
Abstract:
In one embodiment, the present invention includes a method for communicating a request for handling of a fault or exception occurring in an accelerator to a first instruction sequencer coupled thereto. The accelerator may be a heterogeneous resource with respect to the first instruction sequencer, e.g., of a different instruction set architecture. Responsive to the request, the fault or exception may be handled in the first instruction sequencer. Other embodiments are described and claimed.
Public/Granted literature
- US20080005546A1 Handling address translations and exceptions of a heterogeneous resource Public/Granted day:2008-01-03
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