Invention Grant
- Patent Title: Manufacturing method of a multi-layered circuit board
- Patent Title (中): 多层电路板的制造方法
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Application No.: US11297358Application Date: 2005-12-09
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Publication No.: US07488676B2Publication Date: 2009-02-10
- Inventor: Yasuhiko Kanaya , Akira Irie , Katsuhiro Nagasawa , Toru Yuki
- Applicant: Yasuhiko Kanaya , Akira Irie , Katsuhiro Nagasawa , Toru Yuki
- Applicant Address: JP Kanagawa
- Assignee: Hitachi Via Mechanics, Ltd.
- Current Assignee: Hitachi Via Mechanics, Ltd.
- Current Assignee Address: JP Kanagawa
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2004-359169 20041210
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A manufacturing method of a multi-layered circuit board allows electronic parts to be mounted adequately and will not hamper performance of the electronic parts. A power terminal (pin) of an electronic part to be mounted on a surface of the multi-layered circuit board is inserted into a plated through hole to connect with a first conductive layer. A detecting section having a detecting hole which is formed coaxially with the through hole and whose diameter is larger than the through hole is provided on a second conductive layer on the back of the first conductive layer. A hole having a large diameter is formed by a tool along the through hole from the back while applying voltage between the second conductive layer and the tool. The depth of the hole is set based on the tool electrically conducting with the detecting hole. Unnecessary plate of the through hole may be removed by the large hole.
Public/Granted literature
- US20060127652A1 Multi-layered circuit board and manufacturing method of multi-layered circuit board Public/Granted day:2006-06-15
Information query
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