发明授权
- 专利标题： Method of manufacturing interconnect substrate
- 专利标题（中）： 制造互连基板的方法
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申请号： US11716720申请日： 2007-03-09
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公开(公告)号： US07488678B2公开(公告)日： 2009-02-10
- 发明人: Satoshi Kimura , Hidemichi Furihata , Toshihiko Kaneda
- 申请人： Satoshi Kimura , Hidemichi Furihata , Toshihiko Kaneda
- 申请人地址： JP
- 专利权人： Seiko Epson Corporation
- 当前专利权人： Seiko Epson Corporation
- 当前专利权人地址： JP
- 代理机构： Harness, Dickey & Pierce, P.L.C.
- 优先权： JP2006-065988 20060310
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763
摘要：
A method of manufacturing an interconnect substrate by electroless plating, including: (a) forming a catalyst layer with a specific pattern on a substrate; (b) immersing the substrate in a first electroless plating solution including a first metal to deposit the first metal on the catalyst layer to form a first metal layer; and (c) immersing the substrate in a second electroless plating solution including a second metal to deposit the second metal on the first metal layer to form a second metal layer, an ionization tendency of the first metal being higher than an ionization tendency of the second metal.
公开/授权文献
- US20070212871A1 Method of manufacturing interconnect substrate 公开/授权日：2007-09-13
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