发明授权
US07495462B2 Method of wafer-level packaging using low-aspect ratio through-wafer holes
有权
使用低纵横比穿透晶片孔的晶圆级封装方法
- 专利标题: Method of wafer-level packaging using low-aspect ratio through-wafer holes
- 专利标题(中): 使用低纵横比穿透晶片孔的晶圆级封装方法
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申请号: US11505046申请日: 2006-08-16
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公开(公告)号: US07495462B2公开(公告)日: 2009-02-24
- 发明人: Yaping Hua , Zongya Li , Yang Zhao
- 申请人: Yaping Hua , Zongya Li , Yang Zhao
- 申请人地址: US MA North Andover
- 专利权人: Memsic, Inc.
- 当前专利权人: Memsic, Inc.
- 当前专利权人地址: US MA North Andover
- 代理机构: Weingarten, Schurgin, Gagnebin & Lebovici LLP
- 主分类号: G01R31/02
- IPC分类号: G01R31/02
摘要:
A wafer-level packaged IC is made by attaching a cap wafer to the front of an IC base wafer before cutting the IC base wafer, i.e. before singulating the plurality of dies on the IC base wafer. The cap wafer is mechanically attached and electrically connected to the IC base wafer, then the dies are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the front surface of the cap and electrical contact points on the IC base wafer. Optionally, the cap wafer contains one or more dies. The IC base wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without dies) can be stacked to form a “multi-story” IC. Optionally, a hermetically-sealed cavity headroom is provided.
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