公开(公告)号：US07495462B2

公开(公告)日：2009-02-24

申请号：US11505046

申请日：2006-08-16

申请人： Yaping Hua ,  Zongya Li ,  Yang Zhao

发明人： Yaping Hua ,  Zongya Li ,  Yang Zhao

IPC分类号： G01R31/02

CPC分类号： B81C1/00301 ,  B81B2207/097 ,  B81C1/0023 ,  B81C2203/0118 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/1627 ,  H01L2924/163 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A wafer-level packaged IC is made by attaching a cap wafer to the front of an IC base wafer before cutting the IC base wafer, i.e. before singulating the plurality of dies on the IC base wafer. The cap wafer is mechanically attached and electrically connected to the IC base wafer, then the dies are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the front surface of the cap and electrical contact points on the IC base wafer. Optionally, the cap wafer contains one or more dies. The IC base wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without dies) can be stacked to form a “multi-story” IC. Optionally, a hermetically-sealed cavity headroom is provided.

摘要翻译： 在切割IC基片之前，即在IC基片上分离多个管芯之前，将盖晶片附接到IC基片的前部，制成晶片级封装IC。 盖晶片机械地附接并电连接到IC基片，然后将模具分割。 导电路径延伸穿过盖晶片，在盖的前表面上的晶片接触焊盘和IC基片之间的电接触点之间。 可选地，盖晶片包含一个或多个管芯。 可以根据与盖晶片不同的技术制造IC基底晶片，从而形成混合晶片级封装。 可选地，可以堆叠另外的“上层”盖晶片（具有或不具有裸片）以形成“多层”IC。 可选地，提供密封的腔室空间。

公开(公告)号：US20070101813A1

公开(公告)日：2007-05-10

申请号：US11271035

申请日：2005-11-10

申请人： Yaping Hua ,  Leyue Jiang ,  Yongyao Cai ,  Albert Leung ,  Yang Zhao

发明人： Yaping Hua ,  Leyue Jiang ,  Yongyao Cai ,  Albert Leung ,  Yang Zhao

IPC分类号： G01P15/00

CPC分类号： G01P15/18 ,  G01P15/006

摘要： Single chip 3-axis thermal accelerometer devices include a substrate, at least one cavity etched in the substrate, a fluid disposed in the cavity, a bridge structure suspended over an opening of the cavity, and a plurality of heater elements and temperature sensing elements disposed on the bridge structure. The substrate has a substantially planar surface defined by X and Y coordinate axes, and the bridge structure is suspended over the opening of the cavity in the X-Y plane. In one embodiment, the bridge structure is configured to position at least two of the temperature sensing elements out of the X-Y plane. The heater and temperature sensing elements are disposed on the bridge structure in optimized arrangements for providing reduced temperature coefficients and for producing output voltages having reduced DC offset and drift.

摘要翻译： 单芯片3轴热加速度计装置包括衬底，在衬底中蚀刻的至少一个腔，设置在空腔中的流体，悬挂在空腔的开口上的桥结构，以及多个加热器元件和温度感测元件， 在桥梁结构上。 衬底具有由X和Y坐标轴限定的基本平坦的表面，并且桥结构悬挂在X-Y平面中的空腔的开口上。 在一个实施例中，桥结构被配置为将至少两个温度感测元件定位在X-Y平面之外。 加热器和温度感测元件以优化的布置设置在桥结构上，以提供降低的温度系数并且用于产生具有降低的DC偏移和漂移的输出电压。

公开(公告)号：US06712983B2

公开(公告)日：2004-03-30

申请号：US09833973

申请日：2001-04-12

申请人： Yang Zhao ,  Yaping Hua

发明人： Yang Zhao ,  Yaping Hua

IPC分类号： B81C100

CPC分类号： B81C1/00571 ,  H01L21/3065

摘要： A method of etching a trench in a substrate using a dry plasma etch technique that allows precise control of lateral undercut. The method includes optionally forming at least one on-chip device or micro-machined structure in a surface of a silicon substrate, and covering the surface with a masking layer. A trench pattern is then imaged in or transferred to the masking layer for subsequent etching of the substrate. Upper portions of the trench are anisotropically etched in the substrate. The trench is then semi-anisotropically etched and isotropically etched in the substrate. By modifying isotropic etching time, a controlled lateral undercut can be achieved as the trench is etched vertically in the substrate.

摘要翻译： 使用允许精确控制横向底切的干等离子体蚀刻技术来蚀刻衬底中的沟槽的方法。 该方法包括任选地在硅衬底的表面中形成至少一个片上器件或微加工结构，并用掩模层覆盖该表面。 然后将沟槽图案成像在掩模层中或转移到掩模层，以便随后蚀刻衬底。 在衬底中各向异性地蚀刻沟槽的上部。 然后在衬底中对该沟槽进行半各向异性蚀刻和各向同性蚀刻。 通过改变各向同性蚀刻时间，可以在衬底中垂直蚀刻沟槽来实现受控的横向底切。

公开(公告)号：US20060273430A1

公开(公告)日：2006-12-07

申请号：US11505046

申请日：2006-08-16

申请人： Yaping Hua ,  Zongya Li ,  Yang Zhao

发明人： Yaping Hua ,  Zongya Li ,  Yang Zhao

IPC分类号： H01L23/20 ,  H01L21/46

CPC分类号： B81C1/00301 ,  B81B2207/097 ,  B81C1/0023 ,  B81C2203/0118 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/1627 ,  H01L2924/163 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A wafer-level packaged IC is made by attaching a cap wafer to the front of an IC base wafer before cutting the IC base wafer, i.e. before singulating the plurality of dies on the IC base wafer. The cap wafer is mechanically attached and electrically connected to the IC base wafer, then the dies are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the front surface of the cap and electrical contact points on the IC base wafer. Optionally, the cap wafer contains one or more dies. The IC base wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without dies) can be stacked to form a “multi-story” IC. Optionally, a hermetically-sealed cavity headroom is provided.

公开(公告)号：US20100050747A1

公开(公告)日：2010-03-04

申请号：US12229646

申请日：2008-08-26

申请人： Yaping Hua ,  Zongya Li ,  Hanwu Xiao

发明人： Yaping Hua ,  Zongya Li ,  Hanwu Xiao

IPC分类号： G01M3/04

CPC分类号： G01M3/26 ,  G01M3/002 ,  G01P1/023 ,  G01P15/008

摘要： A method and device for identifying leaks in or a leakage rate of an integrated circuit package. The method and device include integrating a micromachined-thermal-convection accelerometer in the integrated circuit package and evaluating the initial and subsequent sensitivities of the accelerometer. A change in sensitivity with time provides indicia of a leak and a measure of leakage rate.

摘要翻译： 一种用于识别集成电路封装的泄漏或泄漏速率的方法和装置。 该方法和装置包括将微加工热对流加速度计集成在集成电路封装中并评估加速度计的初始和随后的灵敏度。 灵敏度随时间的变化提供泄漏的标记和泄漏率的测量。

公开(公告)号：US07424826B2

公开(公告)日：2008-09-16

申请号：US11271035

申请日：2005-11-10

申请人： Yaping Hua ,  Leyue Jiang ,  Yongyao Cai ,  Albert Leung ,  Yang Zhao

发明人： Yaping Hua ,  Leyue Jiang ,  Yongyao Cai ,  Albert Leung ,  Yang Zhao

IPC分类号： G01P15/00

CPC分类号： G01P15/18 ,  G01P15/006

摘要： Single chip 3-axis thermal accelerometer devices include a substrate, at least one cavity etched in the substrate, a fluid disposed in the cavity, a bridge structure suspended over an opening of the cavity, and a plurality of heater elements and temperature sensing elements disposed on the bridge structure. The substrate has a substantially planar surface defined by X and Y coordinate axes, and the bridge structure is suspended over the opening of the cavity in the X-Y plane. In one embodiment, the bridge structure is configured to position at least two of the temperature sensing elements out of the X-Y plane. The heater and temperature sensing elements are disposed on the bridge structure in optimized arrangements for providing reduced temperature coefficients and for producing output voltages having reduced DC offset and drift.

摘要翻译： 单芯片3轴热加速度计装置包括衬底，在衬底中蚀刻的至少一个腔，设置在空腔中的流体，悬挂在空腔的开口上的桥结构，以及多个加热器元件和温度感测元件， 在桥梁结构上。 衬底具有由X和Y坐标轴限定的基本平坦的表面，并且桥结构悬挂在X-Y平面中的空腔的开口上。 在一个实施例中，桥结构被配置为将至少两个温度感测元件定位在X-Y平面之外。 加热器和温度感测元件以优化的布置设置在桥结构上，以提供降低的温度系数并且用于产生具有降低的DC偏移和漂移的输出电压。

公开(公告)号：US08011226B2

公开(公告)日：2011-09-06

申请号：US12229646

申请日：2008-08-26

申请人： Yaping Hua ,  Zongya Li ,  Hanwu Xiao

发明人： Yaping Hua ,  Zongya Li ,  Hanwu Xiao

IPC分类号： G01M3/40

CPC分类号： G01M3/26 ,  G01M3/002 ,  G01P1/023 ,  G01P15/008

摘要： A method and device for identifying leaks in or a leakage rate of an integrated circuit package. The method and device include integrating a micromachined-thermal-convection accelerometer in the integrated circuit package and evaluating the initial and subsequent sensitivities of the accelerometer. A change in sensitivity with time provides indicia of a leak and a measure of leakage rate.

摘要翻译： 一种用于识别集成电路封装的泄漏或泄漏速率的方法和装置。 该方法和装置包括将微加工热对流加速度计集成在集成电路封装中并评估加速度计的初始和随后的灵敏度。 灵敏度随时间的变化提供泄漏的标记和泄漏率的测量。