Invention Grant
- Patent Title: Methods of compensating for an alignment error during fabrication of structures on semiconductor substrates
- Patent Title (中): 在半导体衬底上的结构制造期间补偿对准误差的方法
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Application No.: US11590072Application Date: 2006-10-31
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Publication No.: US07498248B2Publication Date: 2009-03-03
- Inventor: Jung-Taek Lim , Dong-Chun Lee , Young-Jee Yoon , Sung-Hong Park
- Applicant: Jung-Taek Lim , Dong-Chun Lee , Young-Jee Yoon , Sung-Hong Park
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2005-0115326 20051130
- Main IPC: H01L21/3205
- IPC: H01L21/3205

Abstract:
In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure. A second conductive contact structure is formed at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure.
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