公开(公告)号：US07498248B2

公开(公告)日：2009-03-03

申请号：US11590072

申请日：2006-10-31

申请人： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

发明人： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

IPC分类号： H01L21/3205

CPC分类号： G03F7/70633

摘要： In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure. A second conductive contact structure is formed at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure.

摘要翻译： 在半导体衬底上的结构制造期间补偿对准误差的方法中，在第一半导体衬底上的第一位置处形成导电图案结构。 导电图案结构包括布置成列和相交行的第一和第二导电图案的格栅，其间具有开口。 第一导电接触结构与导电图案结构重叠，并且包括布置成可以相对于导电图案结构的格栅非零角度倾斜的行和列格栅的多个间隔开的导电接点。 确定第一导电接触结构是否电连接到导电图案结构。 第二导电接触结构形成在第二半导体衬底上的响应于第一导电接触结构是否电连接到导电图案结构的确定而确定的位置。

公开(公告)号：US20070120220A1

公开(公告)日：2007-05-31

申请号：US11590072

申请日：2006-10-31

申请人： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

发明人： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

IPC分类号： H01L29/00

CPC分类号： G03F7/70633

摘要： In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure. A second conductive contact structure is formed at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure.

摘要翻译： 在半导体衬底上的结构制造期间补偿对准误差的方法中，在第一半导体衬底上的第一位置处形成导电图案结构。 导电图案结构包括布置成列和相交行的第一和第二导电图案的格栅，其间具有开口。 第一导电接触结构与导电图案结构重叠，并且包括布置成可以相对于导电图案结构的格栅非零角度倾斜的行和列格栅的多个间隔开的导电接点。 确定第一导电接触结构是否电连接到导电图案结构。 第二导电接触结构形成在第二半导体衬底上的响应于第一导电接触结构是否电连接到导电图案结构的确定而确定的位置。

公开(公告)号：US07626164B2

公开(公告)日：2009-12-01

申请号：US11564726

申请日：2006-11-29

申请人： Young-Jee Yoon ,  Jung-Taek Lim ,  Tae-Sung Kim ,  Chung-Sam Jun ,  Sung-Hong Park

发明人： Young-Jee Yoon ,  Jung-Taek Lim ,  Tae-Sung Kim ,  Chung-Sam Jun ,  Sung-Hong Park

IPC分类号： G01N23/00

CPC分类号： G01N23/203

摘要： In an embodiment, a method of scanning a substrate, and a method and an apparatus for analyzing crystal characteristics are disclosed. A sequential scan on the scan areas using a first electron beam and a second electron beam are repeatedly performed. The electrons accumulated in the scan areas by the first electron beam are removed from the scan areas by the second electron beam. When a size of the scan area is substantially the same as a spot size of the first electron beam, adjacent scan areas partially overlap each other. When each of the scan areas is larger than a spot size of the first electron beam, the adjacent scan areas do not overlap each other. Images of the scan areas are generated using back-scattered electrons emitted from each of the scan areas by irradiating the first electron beam to analyze crystal characteristics of circuit patterns on the substrate.

摘要翻译： 在一个实施例中，公开了一种扫描衬底的方法，以及用于分析晶体特性的方法和装置。 使用第一电子束和第二电子束对扫描区域进行顺序扫描。 通过第二电子束从扫描区域去除由第一电子束累积在扫描区域中的电子。 当扫描区域的尺寸与第一电子束的光斑尺寸基本相同时，相邻的扫描区域彼此部分重叠。 当每个扫描区域大于第一电子束的光斑尺寸时，相邻的扫描区域彼此不重叠。 通过照射第一电子束来分析从每个扫描区域发射的背散射电子来分析扫描区域的图像，以分析衬底上的电路图案的晶体特性。

公开(公告)号：US07747063B2

公开(公告)日：2010-06-29

申请号：US11463281

申请日：2006-08-08

申请人： Jung-Taek Lim ,  Chung-Sam Jun ,  Young-Jee Yoon ,  Sung-Hong Park

发明人： Jung-Taek Lim ,  Chung-Sam Jun ,  Young-Jee Yoon ,  Sung-Hong Park

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G06T2207/30148 ,  H01J2237/2817

摘要： In an embodiment of a method of inspecting a substrate, the substrate on which minute structures are formed is divided into a plurality of inspection regions. A main inspection region among the inspection regions is selected. A main image of the main inspection region and sub-images of sub-inspection regions adjacent to the main inspection region are obtained. An average image of the main image and the sub-images is obtained. The average image is then compared with the main image to detect defects in the main inspection region. Gray levels may be used. The average image may have improved quality so that the defects in the selected inspection region may be rapidly and accurately detected. This process has an improved reliability. Further, the number of inspecting processes for the substrate may be reduced. And a line for the inspection process may be automated so that a worker-free line may be established.

摘要翻译： 在检查基板的方法的实施例中，其上形成有微小结构的基板被分成多个检查区域。 选择检验区域的主要检验区域。 获得主检查区域的主要图像和与主检查区域相邻的副检查区域的子图像。 获得主图像和子图像的平均图像。 然后将平均图像与主图像进行比较，以检测主检查区域中的缺陷。 可以使用灰度级。 平均图像可以具有改进的质量，使得可以快速和准确地检测所选择的检查区域中的缺陷。 该过程具有改进的可靠性。 此外，可以减少基板的检查过程的数量。 并且检查过程的一行可以是自动化的，从而可以建立无工人行。

公开(公告)号：US20070031025A1

公开(公告)日：2007-02-08

申请号：US11463281

申请日：2006-08-08

申请人： Jung-Taek Lim ,  Chung-Sam Jun ,  Young-Jee Yoon ,  Sung-Hong Park

发明人： Jung-Taek Lim ,  Chung-Sam Jun ,  Young-Jee Yoon ,  Sung-Hong Park

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G06T2207/30148 ,  H01J2237/2817

摘要： In an embodiment of a method of inspecting a substrate, the substrate on which minute structures are formed is divided into a plurality of inspection regions. A main inspection region among the inspection regions is selected. A main image of the main inspection region and sub-images of sub-inspection regions adjacent to the main inspection region are obtained. An average image of the main image and the sub-images is obtained. The average image is then compared with the main image to detect defects in the main inspection region. Gray levels may be used. The average image may have improved quality so that the defects in the selected inspection region may be rapidly and accurately detected. This process has an improved reliability. Further, the number of inspecting processes for the substrate may be reduced. And a line for the inspection process may be automated so that a worker-free line may be established.

摘要翻译： 在检查基板的方法的实施例中，其上形成有微小结构的基板被分成多个检查区域。 选择检验区域的主要检验区域。 获得主检查区域的主要图像和与主检查区域相邻的副检查区域的子图像。 获得主图像和子图像的平均图像。 然后将平均图像与主图像进行比较，以检测主检查区域中的缺陷。 可以使用灰度级。 平均图像可以具有改进的质量，使得可以快速和准确地检测所选择的检查区域中的缺陷。 该过程具有改进的可靠性。 此外，可以减少基板的检查过程的数量。 并且检查过程的一行可以是自动化的，从而可以建立无工人行。

公开(公告)号：US07697130B2

公开(公告)日：2010-04-13

申请号：US12368020

申请日：2009-02-09

申请人： Woo-Seok Ko ,  Yu-Sin Yang ,  Young-Jee Yoon ,  Chung-Sam Jun

发明人： Woo-Seok Ko ,  Yu-Sin Yang ,  Young-Jee Yoon ,  Chung-Sam Jun

IPC分类号： G01N21/88 ,  G06F19/00

CPC分类号： G01N21/9501 ,  G01N2021/8858 ,  G01N2021/8861

摘要： A surface inspection apparatus and method increase wafer productivity, wherein to increase an efficiency of the surface inspection apparatus to detect defects during a scanning of the wafer surface, a scanning speed for a subsequent defect detection is varied according to an increase/decrease of defect density represented on a plurality of images acquired successively. When the density of defects is reduced, the scanning speed increases and a level of a skip rule increases, and when the density of defects increases, the scanning speed decreases and a level of the skip rule decreases to precisely detect defects, thereby increasing reliability, throughput, and productivity.

摘要翻译： 表面检查装置和方法提高晶片生产率，其中为了提高表面检查装置在晶片表面的扫描期间的缺陷的效率，随后的缺陷检测的扫描速度根据缺陷密度的增加/减小而变化 表示在连续获取的多个图像上。 当缺陷密度降低时，扫描速度增加，跳跃规则的水平增加，并且当缺陷密度增加时，扫描速度降低，并且跳过规则的水平降低以精确地检测缺陷，从而提高可靠性， 吞吐量和生产力。

公开(公告)号：US20090219520A1

公开(公告)日：2009-09-03

申请号：US12368020

申请日：2009-02-09

申请人： Woo-Seok Ko ,  Yu-Sin Yang ,  Young-Jee Yoon ,  Chung-Sam Jun

发明人： Woo-Seok Ko ,  Yu-Sin Yang ,  Young-Jee Yoon ,  Chung-Sam Jun

IPC分类号： G01N21/88 ,  G06F19/00

CPC分类号： G01N21/9501 ,  G01N2021/8858 ,  G01N2021/8861

摘要： A surface inspection apparatus and method increase wafer productivity, wherein to increase an efficiency of the surface inspection apparatus to detect defects during a scanning of the wafer surface, a scanning speed for a subsequent defect detection is varied according to an increase/decrease of defect density represented on a plurality of images acquired successively. When the density of defects is reduced, the scanning speed increases and a level of a skip rule increases, and when the density of defects increases, the scanning speed decreases and a level of the skip rule decreases to precisely detect defects, thereby increasing reliability, throughput, and productivity.

摘要翻译： 表面检查装置和方法提高晶片生产率，其中为了提高表面检查装置在晶片表面的扫描期间的缺陷的效率，随后的缺陷检测的扫描速度根据缺陷密度的增加/减小而变化 表示在连续获取的多个图像上。 当缺陷密度降低时，扫描速度增加，跳跃规则的水平增加，并且当缺陷密度增加时，扫描速度降低，并且跳过规则的水平降低以精确地检测缺陷，从而提高可靠性， 吞吐量和生产力。

公开(公告)号：US20050151456A1

公开(公告)日：2005-07-14

申请号：US11028895

申请日：2005-01-04

申请人： Young-Jee Yoon ,  Chung-Sam Jun ,  Sang-Mun Chon

发明人： Young-Jee Yoon ,  Chung-Sam Jun ,  Sang-Mun Chon

IPC分类号： G01R31/302 ,  G01R31/307 ,  H01J1/304 ,  H01J3/02 ,  H01J37/065 ,  H01J37/073 ,  H01L21/66 ,  H01L21/768 ,  H01J1/02 ,  H01J1/14

CPC分类号： B82Y10/00 ,  G01R31/307 ,  H01J1/3042 ,  H01J37/073 ,  H01J2201/30469 ,  H01J2237/0635 ,  H01J2237/2594

摘要： Electron-beam generators have wide area and directional beam generation capability. The generators include anode and cathode electrodes, which are disposed in spaced-apart and opposing relationship relative to each other. A clustered carbon nanotube array is provided to support the wide area and directional beam generation. The clustered nanotube array extends between the anode and cathode electrodes. The nanotube array also has a wide area emission surface thereon, which extends opposite a primary surface of the anode electrode. The clustered nanotube array is configured so that nanotubes therein provide conductive channels for electrons, which pass from the cathode electrode to the anode electrode via the emission surface.

摘要翻译： 电子束发生器具有广泛的面积和定向束产生能力。 发生器包括阳极和阴极电极，它们彼此间隔开和相对地设置。 提供聚簇碳纳米管阵列以支持广域和定向束产生。 聚集的纳米管阵列在阳极和阴极之间延伸。 纳米管阵列还具有与阳极电极的主表面相对延伸的广泛的发射表面。 聚集的纳米管阵列被配置为使得其中的纳米管为电子提供导电通道，电子通过发射表面从阴极电极传递到阳极电极。

公开(公告)号：US20050191768A1

公开(公告)日：2005-09-01

申请号：US11054752

申请日：2005-02-09

申请人： Young-Jee Yoon ,  Chung-Sam Jun ,  Chul-Gi Song ,  Sang-Mun Chon

发明人： Young-Jee Yoon ,  Chung-Sam Jun ,  Chul-Gi Song ,  Sang-Mun Chon

IPC分类号： G01N27/416 ,  G01R31/26 ,  H01L21/4763 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L22/14 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate measuring apparatus includes a reference value storage unit, an electron irradiator, a current measuring device, and a property value calculating device. The reference value storage unit stores data on the relationship between current flow in a sample substrate with a contact hole of known characteristics that is irradiated by an electron beam. The current measuring device measures current flow in a test substrate. The property value calculating device calculates the property value of the contact hole formed in a material layer of the test substrate using the current flow in the test substrate and the data stored in the reference value storage unit. The property values of the contact hole may be a surface area of underlying substrate exposed by a contact hole or an amount of residual material remaining in the contact hole.

摘要翻译： 基板测量装置包括参考值存储单元，电子辐射器，电流测量装置和属性值计算装置。 参考值存储单元存储关于样品基板中的电流与具有由电子束照射的已知特性的接触孔之间的关系的数据。 当前的测量装置测量测试基板中的电流。 属性值计算装置使用测试基板中的电流和存储在参考值存储单元中的数据来计算形成在测试基板的材料层中的接触孔的属性值。 接触孔的特性值可以是由接触孔暴露的下层基板的表面积或残留在接触孔中的残留材料的量。