发明授权
- 专利标题: Implementation of low power standby modes for integrated circuits
- 专利标题(中): 实现集成电路的低功耗待机模式
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申请号: US11268265申请日: 2005-11-04
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公开(公告)号: US07498835B1公开(公告)日: 2009-03-03
- 发明人: Arifur Rahman , Sean W. Kao , Tim Tuan , Patrick J. Crotty , Jinsong Oliver Huang
- 申请人: Arifur Rahman , Sean W. Kao , Tim Tuan , Patrick J. Crotty , Jinsong Oliver Huang
- 申请人地址: US CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: US CA San Jose
- 代理商 William L. Paradice, III; Justin Liu
- 主分类号: H03K19/173
- IPC分类号: H03K19/173 ; G11C5/14
摘要:
A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.
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