发明授权
- 专利标题: Method of manufacturing gate sidewalls that avoids recessing
- 专利标题(中): 制造避免凹陷的栅极侧壁的方法
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申请号: US11422952申请日: 2006-06-08
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公开(公告)号: US07514331B2公开(公告)日: 2009-04-07
- 发明人: Jong Shik Yoon , Amitava Chatterjee , Haowen Bu
- 申请人: Jong Shik Yoon , Amitava Chatterjee , Haowen Bu
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Wad J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.