发明授权
- 专利标题: Asymmetrical layout structure for ESD protection
- 专利标题(中): ESD保护的非对称布局结构
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申请号: US10985532申请日: 2004-11-10
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公开(公告)号: US07518192B2公开(公告)日: 2009-04-14
- 发明人: Kuo-Feng Yu , Jian-Hsing Lee , Jiaw-Ren Shih , Fu Chin Yang
- 申请人: Kuo-Feng Yu , Jian-Hsing Lee , Jiaw-Ren Shih , Fu Chin Yang
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater & Matsil, L.L.P.
- 主分类号: H01L23/62
- IPC分类号: H01L23/62
摘要:
A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.
公开/授权文献
- US20060097330A1 Asymmetrical layout structure for ESD protection 公开/授权日:2006-05-11
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