公开(公告)号：US08704312B2

公开(公告)日：2014-04-22

申请号：US12652294

申请日：2010-01-05

Applicant: Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

Inventor： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L24/16 ,  H01L24/48 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

Abstract translation: 高压（HV）器件包括设置在衬底中的第一掺杂剂类型的阱区。 第二掺杂剂类型的第一阱区域设置在第一掺杂剂类型的阱区域中。 隔离结构至少部分地设置在第一掺杂剂类型的阱区中。 第一栅电极设置在隔离结构和第二掺杂剂类型的第一阱区之上。 第二掺杂剂类型的第二阱区设置在第一掺杂剂类型的阱区中。 第二掺杂剂类型的第二阱区域与第二掺杂剂类型的第一阱区域间隔开。 第二栅电极设置在第二掺杂剂类型的第一阱区域和第二掺杂剂类型的第二阱区域之间和之上。

公开(公告)号：US07869464B2

公开(公告)日：2011-01-11

申请号：US12036678

申请日：2008-02-25

Applicant: Joe Polland ,  Manish Kumar Sharma ,  Xinkuan Zhou ,  Fu-Chin Yang

Inventor： Joe Polland ,  Manish Kumar Sharma ,  Xinkuan Zhou ,  Fu-Chin Yang

IPC: H04J3/00

CPC classification number: H04L12/66 ,  H04M11/062 ,  H04M11/068

Abstract: A communication network comprises a first digital subscriber line (DSL) unit having a plurality of application ports and at least one DSL port; and a second DSL unit having a plurality of application ports and at least one DSL port; wherein the first DSL unit is communicatively coupled to the second DSL unit via a DSL pair coupled to the at least one DSL port in each of the first and second DSL units; and wherein each of the first and second DSL units are configured to receive a signal of a first interface format over one of the plurality of application ports, extract timeslots from the received first interface format signal, transmit the timeslots over the at least one DSL port, and use timeslots received over the at least one DSL port to generate at least one second signal of a dissimilar interface format.

Abstract translation: 通信网络包括具有多个应用端口和至少一个DSL端口的第一数字用户线路（DSL）单元; 以及具有多个应用端口和至少一个DSL端口的第二DSL单元; 其中所述第一DSL单元经由耦合到所述第一和第二DSL单元中的每一个中的所述至少一个DSL端口的DSL对来通信地耦合到所述第二DSL单元; 并且其中所述第一和第二DSL单元中的每一个被配置为在所述多个应用端口之一上接收第一接口格式的信号，从所接收的第一接口格式信号中提取时隙，在所述至少一个DSL端口上传送所述时隙 并且使用通过所述至少一个DSL端口接收的时隙来生成不同接口格式的至少一个第二信号。

公开(公告)号：US20090141640A1

公开(公告)日：2009-06-04

申请号：US11947457

申请日：2007-11-29

Applicant: Joe Polland ,  Fu-Chin Yang ,  Manish Sharma ,  Xinkuan Zhou

Inventor： Joe Polland ,  Fu-Chin Yang ,  Manish Sharma ,  Xinkuan Zhou

IPC: G01R31/08

CPC classification number: H04L12/2881 ,  H04L41/0677 ,  H04L41/0681

Abstract: Systems and methods for communicating faults across a communications network cross-connect are provided. In one embodiment, a method for communicating an alarm condition in a cross-connected network is provided. The method comprises providing a cross-connect having a first side and a second side, wherein the first side includes a plurality of interface ports and the second side includes an interface port; detecting a fault on a first interface port of the first side; and when a fault is detected on the first interface port of the first side, transmitting a signal on the interface port of the second side, the signal having a pre-defined alarm data pattern inserted into one or more time slots associated with the first interface port of the first side.

Abstract translation: 提供了用于在通信网络交叉连接中通信故障的系统和方法。 在一个实施例中，提供了一种用于在交叉连接网络中传达报警条件的方法。 该方法包括提供具有第一侧和第二侧的交叉连接，其中第一侧包括多个接口端口，第二侧包括接口端口; 检测所述第一侧的第一接口端口的故障; 并且当在所述第一侧的所述第一接口端口上检测到故障时，在所述第二侧的接口端口上发送信号，所述信号具有插入到与所述第一接口相关联的一个或多个时隙中的预定义报警数据模式 港口的第一边。

公开(公告)号：US5438254A

公开(公告)日：1995-08-01

申请号：US282180

申请日：1994-07-29

Applicant: Edmond Y. Ho ,  Fu-chin Yang ,  Jung-lung Lin

Inventor： Edmond Y. Ho ,  Fu-chin Yang ,  Jung-lung Lin

IPC: G01R23/20 ,  G01R25/08 ,  G01R31/30 ,  G01R23/02

CPC classification number: G01R23/20 ,  G01R25/08 ,  G01R31/30

Abstract: A phase difference measuring device includes a phase detector, a low-pass filter/voltage controlled oscillator, a reference signal selector for selecting either an internal reference signal or an external reference signal as a reference signal, a phase comparator for comparing an undertest signal with the selected reference signal and obtaining a phase difference between the two compared signal. The internal reference signal is selected when the undertest signal is a jittering signal, and the external reference signal is selected when the undertest signal is a wandering signal. The undertest signal, the selected reference signal, and a relatively high frequency clock signal from external are sent to the phase comparator and a phase difference between the undertest signal and the selected reference signal is counted by the relatively high frequency clock signal.

Abstract translation: 相位差测量装置包括相位检测器，低通滤波器/压控振荡器，用于选择内部参考信号或外部参考信号作为参考信号的参考信号选择器，将相关信号与 所选择的参考信号并获得两个比较信号之间的相位差。 当承载信号为抖动信号时，选择内部参考信号，当承载信号为漫游信号时，选择外部参考信号。 承受信号，所选择的参考信号和来自外部的相对高频时钟信号被发送到相位比较器，并且通过相对高频时钟信号对该信号和所选参考信号之间的相位差进行计数。

公开(公告)号：US08358584B2

公开(公告)日：2013-01-22

申请号：US11947457

申请日：2007-11-29

Applicant: Joe Polland ,  Fu-Chin Yang ,  Manish Sharma ,  Xinkuan Zhou

Inventor： Joe Polland ,  Fu-Chin Yang ,  Manish Sharma ,  Xinkuan Zhou

IPC: G01R31/08

CPC classification number: H04L12/2881 ,  H04L41/0677 ,  H04L41/0681

Abstract: Systems and methods for communicating faults across a communications network cross-connect are provided. In one embodiment, a method for communicating an alarm condition in a cross-connected network is provided. The method comprises providing a cross-connect having a first side and a second side, wherein the first side includes a plurality of interface ports and the second side includes an interface port; detecting a fault on a first interface port of the first side; and when a fault is detected on the first interface port of the first side, transmitting a signal on the interface port of the second side, the signal having a pre-defined alarm data pattern inserted into one or more time slots associated with the first interface port of the first side.

Abstract translation: 提供了用于在通信网络交叉连接中通信故障的系统和方法。 在一个实施例中，提供了一种用于在交叉连接网络中传达报警条件的方法。 该方法包括提供具有第一侧和第二侧的交叉连接，其中第一侧包括多个接口端口，第二侧包括接口端口; 检测所述第一侧的第一接口端口的故障; 并且当在所述第一侧的所述第一接口端口上检测到故障时，在所述第二侧的接口端口上发送信号，所述信号具有插入到与所述第一接口相关联的一个或多个时隙中的预定义报警数据模式 港口的第一边。

公开(公告)号：US07518192B2

公开(公告)日：2009-04-14

申请号：US10985532

申请日：2004-11-10

Applicant: Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

Inventor： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

IPC: H01L23/62

CPC classification number: H01L21/76816 ,  H01L27/0274 ,  H01L29/78

Abstract: A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.

Abstract translation: 提出了一种用于静电放电保护的半导体结构。 半导体结构包括具有衬底，栅极电极，源极区域和漏极区域的接地栅极nMOS（GGNMOS）。 在源极和漏极侧形成多个接触插塞。 多个第一级通孔电耦合到GGNMOS并且在源极和漏极区域中具有基本不对称的布局。 第二级通过将ESD电流重新路由到期望的第一级通孔。 GGNMOS中电流的均匀性得到改善。

公开(公告)号：US20080205449A1

公开(公告)日：2008-08-28

申请号：US12036678

申请日：2008-02-25

Applicant: Joe Polland ,  Manish Kumar Sharma ,  Xinkuan Zhou ,  Fu-Chin Yang

Inventor： Joe Polland ,  Manish Kumar Sharma ,  Xinkuan Zhou ,  Fu-Chin Yang

IPC: H04J1/00

CPC classification number: H04L12/66 ,  H04M11/062 ,  H04M11/068

Abstract: A communication network comprises a first digital subscriber line (DSL) unit having a plurality of application ports and at least one DSL port; and a second DSL unit having a plurality of application ports and at least one DSL port; wherein the first DSL unit is communicatively coupled to the second DSL unit via a DSL pair coupled to the at least one DSL port in each of the first and second DSL units; and wherein each of the first and second DSL units are configured to receive a signal of a first interface format over one of the plurality of application ports, extract timeslots from the received first interface format signal, transmit the timeslots over the at least one DSL port, and use timeslots received over the at least one DSL port to generate at least one second signal of a dissimilar interface format.

Abstract translation: 通信网络包括具有多个应用端口和至少一个DSL端口的第一数字用户线路（DSL）单元; 以及具有多个应用端口和至少一个DSL端口的第二DSL单元; 其中所述第一DSL单元经由耦合到所述第一和第二DSL单元中的每一个中的所述至少一个DSL端口的DSL对来通信地耦合到所述第二DSL单元; 并且其中所述第一和第二DSL单元中的每一个被配置为在所述多个应用端口之一上接收第一接口格式的信号，从所接收的第一接口格式信号中提取时隙，在所述至少一个DSL端口上传送所述时隙 并且使用通过所述至少一个DSL端口接收的时隙来生成不同接口格式的至少一个第二信号。

公开(公告)号：US20080137244A1

公开(公告)日：2008-06-12

申请号：US11637108

申请日：2006-12-12

Applicant: Kuo-Feng Yo ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu-Chin Yang

Inventor： Kuo-Feng Yo ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu-Chin Yang

IPC: H02H9/00

CPC classification number: H01L27/0262

Abstract: An electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a silicon controlled rectifier (SCR) device and a metal-oxide-semiconductor (MOS) triggering device. The SCR device has a cathode connected to a first fixed potential and an anode. The MOS triggering device has a gate and a source connected to the first fixed potential and a drain connected to the anode. In addition, the MOS triggering device is not physically disposed in the SCR device.

Abstract translation: 静电放电（ESD）保护电路。 ESD保护电路包括可控硅整流器（SCR）器件和金属氧化物半导体（MOS）触发器件。 SCR器件具有连接到第一固定电位和阳极的阴极。 MOS触发装置具有连接到第一固定电位的栅极和源极以及连接到阳极的漏极。 此外，MOS触发装置没有物理地设置在SCR装置中。

公开(公告)号：US20110163376A1

公开(公告)日：2011-07-07

申请号：US12652294

申请日：2010-01-05

Applicant: Chih-Chang CHENG ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

Inventor： Chih-Chang CHENG ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L24/16 ,  H01L24/48 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

Abstract translation: 高压（HV）器件包括设置在衬底中的第一掺杂剂类型的阱区。 第二掺杂剂类型的第一阱区域设置在第一掺杂剂类型的阱区域中。 隔离结构至少部分地设置在第一掺杂剂类型的阱区中。 第一栅电极设置在隔离结构和第二掺杂剂类型的第一阱区之上。 第二掺杂剂类型的第二阱区设置在第一掺杂剂类型的阱区中。 第二掺杂剂类型的第二阱区域与第二掺杂剂类型的第一阱区域间隔开。 第二栅电极设置在第二掺杂剂类型的第一阱区域和第二掺杂剂类型的第二阱区域之间和之上。

公开(公告)号：US07309905B2

公开(公告)日：2007-12-18

申请号：US11065848

申请日：2005-02-25

Applicant: Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

Inventor： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

IPC: H01L29/00 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L29/7436 ,  H01L29/74

Abstract: A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device comprises at least an N-well for providing a high resistance and a P+ material to be used as a collector thereof for further providing a high resistance. At least an Nmoat guard ring and a Pmoat guard ring surround the bipolar device, wherein when an ESD event occurs, the high resistance provided by the N-well and the P+ material of the bipolar device increases a turn-on speed.

Abstract translation: 公开了一种用于实现用于静电放电（ESD）保护的新的基于双极的可控硅整流器（SCR）电路的系统和方法。 SCR电路包括要形成在半导体衬底上的双极器件。 双极器件至少包括用于提供高电阻的N阱和用作集电极的P +材料以进一步提供高电阻。 至少一个Nmoat保护环和Pmoat保护环围绕双极器件，其中当ESD事件发生时，由N阱和双极器件的P +材料提供的高电阻增加了接通速度。