发明授权
US07518398B1 Integrated circuit with through-die via interface for die stacking
有权
集成电路,具有通孔接口,用于芯片堆叠
- 专利标题: Integrated circuit with through-die via interface for die stacking
- 专利标题(中): 集成电路,具有通孔接口,用于芯片堆叠
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申请号: US11973062申请日: 2007-10-04
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公开(公告)号: US07518398B1公开(公告)日: 2009-04-14
- 发明人: Arifur Rahman , Stephen M. Trimberger , Bernard J. New
- 申请人: Arifur Rahman , Stephen M. Trimberger , Bernard J. New
- 申请人地址: US CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: US CA San Jose
- 代理商 Robert M. Brush
- 主分类号: H03K19/173
- IPC分类号: H03K19/173
摘要:
An integrated circuit with a through-die via (TDV) interface for die stacking is described. One aspect of the invention relates to an integrated circuit die having an array of tiles arranged in columns. The integrated circuit die includes at least one interface tile. Each interface tile includes a logic element, contacts, and through die vias (TDVs). The logic element is coupled to a routing fabric of the integrated circuit die. The contacts are configured to be coupled to conductive interconnect of another integrated circuit die attached to the backside of the integrated circuit die. The TDVs are configured to couple the logic element to the contacts.
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