发明授权
US07519780B2 System and method for reducing store latency in symmetrical multiprocessor systems
有权
用于在对称多处理器系统中减少存储延迟的系统和方法
- 专利标题: System and method for reducing store latency in symmetrical multiprocessor systems
- 专利标题(中): 用于在对称多处理器系统中减少存储延迟的系统和方法
-
申请号: US11556346申请日: 2006-11-03
-
公开(公告)号: US07519780B2公开(公告)日: 2009-04-14
- 发明人: Jonathan J. DeMent , Roy M. Kim , Alvan W. Ng , Kevin C. Stelzer , Thuong Q. Truong
- 申请人: Jonathan J. DeMent , Roy M. Kim , Alvan W. Ng , Kevin C. Stelzer , Thuong Q. Truong
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Stephen J. Walder, Jr.; Matthew B. Talpis
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.
公开/授权文献
信息查询