发明授权
US07521776B2 Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers
有权
使用掩埋复合中心的具有混合晶体取向的衬底上的CMOS电路的软误差降低
- 专利标题: Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers
- 专利标题(中): 使用掩埋复合中心的具有混合晶体取向的衬底上的CMOS电路的软误差降低
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申请号: US11618346申请日: 2006-12-29
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公开(公告)号: US07521776B2公开(公告)日: 2009-04-21
- 发明人: Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
- 申请人: Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Scully, Scott, Murphy & Presser, P.C.
- 代理商 Richard M. Kotulak, Esq.
- 主分类号: H01L29/04
- IPC分类号: H01L29/04
摘要:
Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
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