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公开(公告)号：US09165917B2
公开(公告)日：2015-10-20
申请号：US12473409
申请日：2009-05-28
申请人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
发明人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
IPC分类号： H01L27/11 , H01L27/02 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
摘要翻译： 一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。 与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进 具有跨越两个晶体管的相对较小的立体角。 这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。
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公开(公告)号：US08354858B2
公开(公告)日：2013-01-15
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。
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公开(公告)号：US20120122260A1
公开(公告)日：2012-05-17
申请号：US13357728
申请日：2012-01-25
IPC分类号： H01L31/18
CPC分类号： H01L31/115 , H01L23/552 , H01L23/556 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).
摘要翻译： 辐射传感器或检测器阵列集成在三维半导体IC内。 传感器阵列相对靠近电路（例如，微处理器）的器件层定位，以防止电离辐射粒子的不利影响。 因此，辐射粒子与器件层相交的位置可以用粗精度（例如，在10微米以内）来计算。
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公开(公告)号：US08120131B2
公开(公告)日：2012-02-21
申请号：US12547519
申请日：2009-08-26
IPC分类号： H01L31/02
CPC分类号： H01L31/115 , H01L23/552 , H01L23/556 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).
摘要翻译： 辐射传感器或检测器阵列集成在三维半导体IC内。 传感器阵列相对靠近电路（例如，微处理器）的器件层定位，以防止电离辐射粒子的不利影响。 因此，辐射粒子与器件层相交的位置可以用粗精度（例如，在10微米以内）来计算。
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5.发明授权Method and apparatus for reducing radiation and cross-talk induced data errors 有权减少辐射和串扰引起的数据错误的方法和装置公开(公告)号：US08054099B2
公开(公告)日：2011-11-08
申请号：US12511207
申请日：2009-07-29
IPC分类号： H03K19/003 , H03K19/00 , G11C11/00
CPC分类号： G11C5/005 , G11C7/02 , H03K3/0375 , H03K3/356121 , H03K17/693
摘要： The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.
摘要翻译： 不同的有利实施例提供了包括多个锁存器和多个滤波器的集成电路。 锁存器数量中的每个锁存器具有多个输入和多个存储节点。 多个存储节点包括形成多个可压缩电路节点对的多对电路节点。 多个输入的每个输入连接到多个存储节点中的对应的存储节点。 多个滤波器中的每个滤波器具有输入和多个输出。 多个输出中的每一个连接到锁存器数量的锁存器的多个输入的相应输入端。 滤波器数量中的每个滤波器位于两个电路节点之间，形成锁存器数量的锁存器的可升高电路节点对以增加关键节点间隔。
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公开(公告)号：US07888959B2
公开(公告)日：2011-02-15
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。
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公开(公告)号：US20100301446A1
公开(公告)日：2010-12-02
申请号：US12473409
申请日：2009-05-28
申请人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
发明人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
摘要翻译： 一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。 与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进 具有跨越两个晶体管的相对较小的立体角。 这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。
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8.发明申请Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit 有权使用开关电容电路的批量CMOS中的Qcrit测量方法公开(公告)号：US20100271057A1
公开(公告)日：2010-10-28
申请号：US11679406
申请日：2007-02-27
IPC分类号： G01R31/30
CPC分类号： G01R31/318594 , G01R31/318597
摘要： A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.
摘要翻译： 用于估计被测电路的临界电荷的测试装置（CUT）使用具有选择性地连接到CUT的节点的开关电容器的电荷注入电路。 电压测量电路测量电荷注入前后电荷注入电路中的电压。 当注入的电荷导致CUT的逻辑状态不正常时，临界电荷被计算为电压差和电容器的已知电容的乘积。 在一个实施例中，（NMOS漏极击穿模拟）通过门控电荷注入电路的开关的可变脉冲宽度发生器来控制注入的电荷量。 在另一实施例（PMOS漏极击穿模拟）中，注入的电荷量由选择性地连接到电荷存储节点的可变电压电源来控制。
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9.发明申请DESIGN STRUCTURE FOR ALPHA PARTICLE SENSOR IN SOI TECHNOLOGY AND STRUCTURE THEREOF 有权SOI技术中ALPHA粒子传感器的设计结构及其结构公开(公告)号：US20090250622A1
公开(公告)日：2009-10-08
申请号：US12099307
申请日：2008-04-08
IPC分类号： G01T1/24
CPC分类号： H01L31/115
摘要： The invention relates to a design structure, and more particularly, to a design structure for an alpha particle sensor in SOI technology and a circuit thereof. The structure is a silicon-on-insulator radiation detector which includes: a charge collection node; a precharge transistor that has a source from the charge collection node, a drain at Vdd, and a gate controlled by a precharge signal; an access transistor that has a source from the charge collection node, a drain connecting to a readout node, and a gate controlled by a read-out signal; and a detector pulldown transistor having a drain from the charge collection node, a source to ground, and a grounded gate.
摘要翻译： 本发明涉及一种设计结构，更具体地说，涉及SOI技术中的α粒子传感器及其电路的设计结构。 该结构是绝缘体上硅辐射检测器，其包括：电荷收集节点; 具有来自电荷收集节点的源极，Vdd处的漏极以及由预充电信号控制的栅极的预充电晶体管; 具有来自电荷收集节点的源极，与读出节点连接的漏极和由读出信号控制的栅极的存取晶体管; 以及检测器下拉晶体管，其具有来自电荷收集节点的漏极，源极接地和接地栅极。
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10.发明申请SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS 有权使用BURIED重组中心使用混合晶体方位的基板上CMOS电路的软错误减少公开(公告)号：US20080157202A1
公开(公告)日：2008-07-03
申请号：US11618346
申请日：2006-12-29
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L29/1083
摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。
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