A system, apparatus and method enabling common memory pool tests to be conducted in a multiprocessing system by using substantially the same system components that are used during a normal mode of operation. Under normal mode of operation, a data cache interface facilitates data transfer between processors of a multiprocessor system and the common memory pool. In test mode of operation, an integrated data cache exerciser assumes control of the data cache interface to facilitate test data write and read operations to/from the common memory pool. Test data may be generated from data queues within the multiprocessing system that are also operational during normal mode of operation. Alternatively, the test data may be generated from the address used to access the common memory pool.