公开(公告)号：US20100162269A1

公开(公告)日：2010-06-24

申请号：US12340838

申请日：2008-12-22

申请人： Gary J. Lucas ,  Paul S. Neuman

发明人： Gary J. Lucas ,  Paul S. Neuman

IPC分类号： G06F9/44

CPC分类号： G06F11/3495 ,  G06F11/0793 ,  G06F11/3409 ,  G06F11/3476 ,  G06F2201/86

摘要： An apparatus and method are provided for describing the interaction between event monitoring subsystems. A plurality of interactively-connected event monitoring subsystems in a computing system are configured. Events are collected by a first event monitoring subsystem of the plurality of event monitoring subsystems. Additional event information regarding one or more additional events are collected by the one or more second event monitoring systems. This additional information is received at the first event monitoring subsystem from one or more second event monitoring subsystems. An action is also triggered by the first event monitoring subsystem. The action is based on one or both of the collected performance events and the additional performance event information.

摘要翻译： 提供了一种用于描述事件监视子系统之间的交互的装置和方法。 配置计算系统中的多个交互式连接的事件监视子系统。 事件由多个事件监视子系统的第一事件监视子系统收集。 关于一个或多个附加事件的附加事件信息由一个或多个第二事件监视系统收集。 该附加信息在第一事件监视子系统从一个或多个第二事件监视子系统接收。 第一个事件监视子系统也会触发一个动作。 该操作基于收集的性能事件和附加性能事件信息中的一个或两个。

公开(公告)号：US20090313526A1

公开(公告)日：2009-12-17

申请号：US10922206

申请日：2004-08-19

申请人： Paul S. Neuman

发明人： Paul S. Neuman

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/10

摘要： An apparatus and method for selectively deriving Error Correction Codes (ECCs) or other data integrity information for integration into merged data blocks. First data is merged into second data that is error-protected using an ECC generated by a coding algorithm. Bytes or other data units are identified in the first data to be merged into the second data. It is determined whether each of the check bits of the ECC will differ from its original state in response to merging the first and second data. The check bits of the ECC that have been determined to differ from their respective original states are modified to create a “merged ECC.” The resulting data block includes the merged data and the merged ECC.

摘要翻译： 用于选择性地导出纠错码（ECC）或其他数据完整性信息以用于集成到合并的数据块中的装置和方法。 第一数据被合并到使用由编码算法生成的ECC的错误保护的第二数据。 在要合并到第二数据的第一数据中标识字节或其他数据单元。 响应于合并第一和第二数据，确定ECC的每个校验位是否与其原始状态不同。 已经确定为不同于它们各自的原始状态的ECC的校验位被修改以创建“合并的ECC”。 所得到的数据块包括合并的数据和合并的ECC。

公开(公告)号：US07797609B2

公开(公告)日：2010-09-14

申请号：US10922206

申请日：2004-08-19

申请人： Paul S. Neuman

发明人： Paul S. Neuman

IPC分类号： H03M13/00

CPC分类号： G06F11/10

摘要： An apparatus and method for selectively deriving Error Correction Codes (ECCs) or other data integrity information for integration into merged data blocks. First data is merged into second data that is error-protected using an ECC generated by a coding algorithm. Bytes or other data units are identified in the first data to be merged into the second data. It is determined whether each of the check bits of the ECC will differ from its original state in response to merging the first and second data. The check bits of the ECC that have been determined to differ from their respective original states are modified to create a “merged ECC.” The resulting data block includes the merged data and the merged ECC.

摘要翻译： 用于选择性地导出纠错码（ECC）或其他数据完整性信息以用于集成到合并的数据块中的装置和方法。 第一数据被合并到使用由编码算法生成的ECC的错误保护的第二数据。 在要合并到第二数据的第一数据中标识字节或其他数据单元。 响应于合并第一和第二数据，确定ECC的每个校验位是否与其原始状态不同。 已经确定不同于它们各自的原始状态的ECC的校验位被修改以创建“合并的ECC”。所得到的数据块包括合并的数据和合并的ECC。

公开(公告)号：US07069391B1

公开(公告)日：2006-06-27

申请号：US09650800

申请日：2000-08-30

申请人： Paul S. Neuman

发明人： Paul S. Neuman

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0831

摘要： A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from invalidating level one cache information based upon a level one cache memory write. Similarly, the invalidation can occur from system bus SNOOPs. In addition, level one and level two cache memory misses result in loading and recording of the requested data into both level one and level two cache memories. Furthermore, a level two cache memory parity error results in invalidation of the corresponding level one cache memory data.

摘要翻译： 一种用于提高采用多级高速缓冲存储器系统的数据处理系统的效率的方法和装置。 效率是由于基于一级缓存存储器写入而使一级缓存信息无效。 类似地，无效可以从系统总线SNOOP发生。 另外，一级和二级高速缓存存储器未命中导致将请求的数据加载和记录到一级和二级缓存中。 此外，二级缓存存储器奇偶校验错误导致对应的一级缓存存储器数据的无效。

公开(公告)号：US07529890B1

公开(公告)日：2009-05-05

申请号：US10926258

申请日：2004-08-25

申请人： Paul S. Neuman ,  Lloyd P. Dalton

发明人： Paul S. Neuman ,  Lloyd P. Dalton

IPC分类号： G06F12/00

CPC分类号： G06F11/2236

摘要： A system, apparatus and method enabling common memory pool tests to be conducted in a multiprocessing system by using substantially the same system components that are used during a normal mode of operation. Under normal mode of operation, a data cache interface facilitates data transfer between processors of a multiprocessor system and the common memory pool. In test mode of operation, an integrated data cache exerciser assumes control of the data cache interface to facilitate test data write and read operations to/from the common memory pool. Test data may be generated from data queues within the multiprocessing system that are also operational during normal mode of operation. Alternatively, the test data may be generated from the address used to access the common memory pool.

摘要翻译： 通过使用在正常操作模式下使用的基本上相同的系统组件，能够在多处理系统中进行通用存储池测试的系统，装置和方法。 在正常操作模式下，数据高速缓存接口便于多处理器系统的处理器和公共存储器池之间的数据传输。 在测试操作模式下，集成的数据高速缓存练习器假定控制数据高速缓存接口，以方便从公共内存池进行测试数据写入和读取操作。 可以在多处理系统内的数据队列生成测试数据，这些数据队列在正常操作模式下也可操作。 或者，可以从用于访问公共存储器池的地址生成测试数据。

公开(公告)号：US07631132B1

公开(公告)日：2009-12-08

申请号：US11023137

申请日：2004-12-27

申请人： Paul S. Neuman

发明人： Paul S. Neuman

IPC分类号： G06F12/00 ,  G06F13/362 ,  G06F13/00 ,  G06F9/44 ,  G06F11/00

CPC分类号： G06F9/545 ,  G06F9/3855 ,  G06F9/544 ,  G06F13/4059

摘要： A first queue receives transactions from a transaction source in first-in/first-out (FIFO) order regardless of priority. A second queue receives lower priority transactions from the first queue as compared to the higher priority transactions remaining in the first queue. A priority check module controls the forwarding schedule of transactions from the first and second queues in accordance with the associated priorities of the stored transactions. Should an address conflict arise between transactions in the first and second queues, the priority check module stalls forwarding from the first queue while promoting forwarding from the second queue during the conflict condition.

摘要翻译： 第一个队列以先入先出（FIFO）顺序从事务源接收事务，无论优先级如何。 与第一个队列中剩余的较高优先级事务相比，第二个队列从第一个队列接收较低优先级的事务。 优先级检查模块根据存储的事务的相关优先级来控制来自第一和第二队列的事务的转发调度。 如果在第一和第二队列中的事务之间出现地址冲突，则优先级检查模块在冲突条件期间从第一队列转发转移从第二队列转移。

公开(公告)号：US07600143B1

公开(公告)日：2009-10-06

申请号：US10922214

申请日：2004-08-19

申请人： Paul S. Neuman

发明人： Paul S. Neuman

IPC分类号： G06F1/04

CPC分类号： G06F7/06 ,  G06F2205/065 ,  G06F2205/108

摘要： A method and apparatus allows data to traverse a cache interface device in one of four transfer modes. A fast bypass mode provides received cache data within the same master clock cycle as it was received, whereas a slow bypass mode provides received cache data within the subsequent master clock cycle. A queue mode provides a programmable amount of delay to be used by the cache interface device, whereby consecutive queue mode provides a First In First Out (FIFO) operation to consecutively retrieve queued data. A block queue mode, on the other hand, provides a method to retrieve queued data using a programmable offset so as to enable partial cache line retrieval without the need to use No Operation (NoP) clock cycles on the cache interface data bus.

摘要翻译： 一种方法和装置允许数据以四种传输模式之一穿过高速缓存接口设备。 快速旁路模式在与其接收的相同的主时钟周期内提供接收的高速缓存数据，而慢速旁路模式在随后的主时钟周期内提供接收到的高速缓存数据。 队列模式提供由缓存接口设备使用的可编程延迟量，由此连续队列模式提供先进先出（FIFO）操作以连续检索排队的数据。 另一方面，块队列模式提供了一种使用可编程偏移量来检索排队数据的方法，以便在高速缓存接口数据总线上不需要使用无操作（NoP）时钟周期来实现部分高速缓存行检索。

公开(公告)号：US07363440B1

公开(公告)日：2008-04-22

申请号：US11026843

申请日：2004-12-30

申请人： Paul S. Neuman

发明人： Paul S. Neuman

IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F13/22

CPC分类号： G06F13/16

摘要： A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maintenance system. When the scan is complete, the information is collectively transferred to an access register bank. Based on the control signals, a selection multiplexer selects the information from the control scan chain provided by the maintenance system as opposed to standard signals generated by the computer system. Memory control input signals are generated in response to a clock trigger signal, and the read or write data transfer is initiated.

摘要翻译： 一种用于在正常操作条件下动态访问存储器的系统和方法，而不中断否则执行的计算机系统时钟。 至少存储器访问模式和存储器地址从维护系统扫描到控制扫描链中。 当扫描完成时，信息被集体传送到访问寄存器组。 基于控制信号，选择多路复用器从维护系统提供的控制扫描链中选择信息，而不是由计算机系统产生的标准信号。 响应于时钟触发信号产生存储器控制输入信号，并且启动读或写数据传输。