A method of manufacturing an electronic device, which can obtain sufficient manufacturing margins and reduce a defect rate by compensating for a threshold voltage variation caused by the variation of a critical dimension (CD) of a gate electrode. An ion implanter controller and an ion implantation system perform the method. In the method, an ion implantation recipe for forming a junction contact plug of a transistor formed on the wafer is adjusted based on the measured CD. Then, ions are implanted into the wafer by using the adjusted ion implantation recipe. All defects that may occur in the transistor during previous manufacturing steps can be repaired after the transistor is formed, thus enhancing manufacturing margins.