发明授权
US07541240B2 Integration process flow for flash devices with low gap fill aspect ratio 有权
具有低间隙填充宽高比的闪存器件的集成工艺流程

Integration process flow for flash devices with low gap fill aspect ratio
摘要:
A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.
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