公开(公告)号：US20080144384A1

公开(公告)日：2008-06-19

申请号：US12031640

申请日：2008-02-14

申请人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

发明人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  H01L23/5222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US07541240B2

公开(公告)日：2009-06-02

申请号：US11254142

申请日：2005-10-18

申请人： Tuan D. Pham ,  Masaaki Higashitani

发明人： Tuan D. Pham ,  Masaaki Higashitani

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/31111 ,  H01L21/3212 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11531

摘要： A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.

摘要翻译： 形成在浮动栅极之间具有浅沟槽隔离结构并且具有在浮动栅极之间延伸的控制栅极的非易失性存储器，其中浅沟槽隔离电介质被蚀刻。 使用离子注入实现蚀刻深度的控制，以与下层电介质相比形成具有高蚀刻速率的电介质层。 在植入期间，导电层覆盖衬底。 存储器阵列中具有小的多晶硅特征的基板和外围区域中的大多晶硅特征使用周边区域中的突起精细地平坦化，并且当突起被去除时停止的软化学机械抛光步骤。

公开(公告)号：US07436703B2

公开(公告)日：2008-10-14

申请号：US11319908

申请日：2005-12-27

申请人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

发明人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US07362615B2

公开(公告)日：2008-04-22

申请号：US11319260

申请日：2005-12-27

申请人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

发明人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  H01L23/5222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US5920786A

公开(公告)日：1999-07-06

申请号：US60894

申请日：1998-05-14

申请人： Tuan D. Pham ,  Michael K. Templeton

发明人： Tuan D. Pham ,  Michael K. Templeton

IPC分类号： G03F7/00 ,  G03F7/20 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L29/68 ,  G03C5/00 ,  G03F9/00

CPC分类号： H01L21/3086 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/3065 ,  H01L21/76232

摘要： The present invention provides a method of constructing trenches for use in microelectronic circuit structures. A photolithographic method is used to create trenches with sloped walls shaping the photoresist masks into sloped profiles. These photoresist masks effectively shape the underlying substrate during subsequent etch steps producing sloped wall trenches. These trenches can be used as shallow trench isolation structures to isolate microelectronic circuit structures from each other.

摘要翻译： 本发明提供一种构建用于微电子电路结构的沟槽的方法。 使用光刻方法来产生具有将光致抗蚀剂掩模成形为倾斜轮廓的倾斜壁的沟槽。 这些光致抗蚀剂掩模在随后的蚀刻步骤中有效地塑造下面的衬底，产生倾斜的壁沟槽。 这些沟槽可以用作浅沟槽隔离结构，以隔离微电子电路结构。

公开(公告)号：US07012008B1

公开(公告)日：2006-03-14

申请号：US09728554

申请日：2000-12-01

申请人： Jeffrey A. Shields ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Yu Sun ,  Angela T. Hui ,  Maria Chow Chan

发明人： Jeffrey A. Shields ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Yu Sun ,  Angela T. Hui ,  Maria Chow Chan

IPC分类号： H01L21/31

CPC分类号： H01L27/11568 ,  H01L27/11526 ,  H01L27/11531

摘要： In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device. Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.

摘要翻译： 在用于非易失性存储器件的两步间隔件制造工艺中，薄的氧化物层沉积在晶片衬底上，在非易失性存储器件的芯中留下间隙。 可通过该间隙实现植入和/或氧化氮化物 - 氧化物去除。 植入后，沉积第二间隔物。 在第二间隔物沉积之后，执行外围间隔物蚀刻。 通过上述方法，形成间隔物。

公开(公告)号：US20090155967A1

公开(公告)日：2009-06-18

申请号：US11958941

申请日：2007-12-18

申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai ,  Tuan D. Pham

发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai ,  Tuan D. Pham

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42332 ,  Y10S438/962 ,  Y10S977/72 ,  Y10S977/81 ,  Y10S977/943

摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

摘要翻译： 提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。 在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。 将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。 然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。 纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。 在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

公开(公告)号：US06034394A

公开(公告)日：2000-03-07

申请号：US992950

申请日：1997-12-18

申请人： Mark Ramsbey ,  Tuan D. Pham ,  Yu Sun ,  Kenneth W. Au

发明人： Mark Ramsbey ,  Tuan D. Pham ,  Yu Sun ,  Kenneth W. Au

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

摘要翻译： 提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。 通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。 改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。 控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。 裂纹通常发生在半导体器件的随后热处理期间。 因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

公开(公告)号：US5966618A

公开(公告)日：1999-10-12

申请号：US36288

申请日：1998-03-06

申请人： Yu Sun ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Chi Chang

发明人： Yu Sun ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Chi Chang

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L27/105

CPC分类号： H01L21/76221 ,  H01L27/105

摘要： A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

摘要翻译： 提供厚且薄的氧化物结构的方法减小了集成电路上的芯区域和周边区域之间的阶跃变化。 在闪速存储器件的核心区域中提供了薄的LOCOS结构，并且在闪速存储器件的外围区域中提供了厚的LOCOS结构。 设备和过程不容易受到“赛道”问题，“氧化物”碰撞问题和“纵梁”问题的影响。 该方法利用两个分开的氮化物或硬掩模层。

公开(公告)号：US08193055B1

公开(公告)日：2012-06-05

申请号：US11958875

申请日：2007-12-18

申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai ,  Tuan D. Pham

发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai ,  Tuan D. Pham

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/11521 ,  H01L29/42332 ,  Y10S977/72 ,  Y10S977/81

摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, metal salt ions are added to a core of a copolymer solution. A metal salt reduction causes the metal atoms to aggregate in the core, forming a metal nanodot. The copolymer solution is applied to a gate oxide on a substrate using spin coating or dip coating. Due to the copolymer configuration, the nanodots are held in a uniform 2D grid on the gate oxide. The polymers are selected to provide a desired nanodot size and spacing between nanodots. A polymer cure and removal process leaves the nanodots on the gate oxide. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

摘要翻译： 提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。 在一个示例性方法中，将金属盐离子加入到共聚物溶液的芯中。 金属盐还原导致金属原子在芯中聚集，形成金属纳米点。 使用旋涂或浸涂将共聚物溶液施加到基板上的栅极氧化物上。 由于共聚物构型，纳米点被保持在栅极氧化物上的均匀的2D栅格中。 选择聚合物以在纳米点之间提供期望的纳米尺寸和间隔。 聚合物固化和去除过程使栅极氧化物上的纳米点离开。 在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。