Invention Grant
US07544564B2 Method of forming gate electrode pattern in semiconductor device 失效
在半导体器件中形成栅电极图案的方法

Method of forming gate electrode pattern in semiconductor device
Abstract:
A method for forming a semiconductor device includes forming a gate dielectric layer over a substrate; forming a first conductive layer over the substrate; forming a dielectric layer over the first conductive layer; forming a second conductive layer over the dielectric layer; forming a sacrificial layer over the second conductive layer; patterning the sacrificial and other layers to form a plurality of gate electrode patterns; forming a buried oxide layer over and between the gate electrode patterns; and removing the sacrificial layer to form a plurality of trenches surrounded by the buried oxide layer. A metal layer is formed within the trench to form a plurality of metal gate structures, the metal layer contacting the second conductive layer that is exposed by the removal of the sacrificial layer.
Public/Granted literature
Information query
Patent Agency Ranking
0/0