Invention Grant
- Patent Title: Method of forming gate electrode pattern in semiconductor device
- Patent Title (中): 在半导体器件中形成栅电极图案的方法
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Application No.: US11297885Application Date: 2005-12-09
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Publication No.: US07544564B2Publication Date: 2009-06-09
- Inventor: Sung Hoon Lee
- Applicant: Sung Hoon Lee
- Applicant Address: KR Icheon-si
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-si
- Agency: Townsend and Townsend and Crew LLP
- Priority: KR10-2005-0019643 20050309
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for forming a semiconductor device includes forming a gate dielectric layer over a substrate; forming a first conductive layer over the substrate; forming a dielectric layer over the first conductive layer; forming a second conductive layer over the dielectric layer; forming a sacrificial layer over the second conductive layer; patterning the sacrificial and other layers to form a plurality of gate electrode patterns; forming a buried oxide layer over and between the gate electrode patterns; and removing the sacrificial layer to form a plurality of trenches surrounded by the buried oxide layer. A metal layer is formed within the trench to form a plurality of metal gate structures, the metal layer contacting the second conductive layer that is exposed by the removal of the sacrificial layer.
Public/Granted literature
- US20060205160A1 Method of forming gate electrode pattern in semiconductor device Public/Granted day:2006-09-14
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