Invention Grant
US07544569B2 Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
有权
双向分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
- Patent Title: Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
- Patent Title (中): 双向分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
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Application No.: US11516431Application Date: 2006-09-05
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Publication No.: US07544569B2Publication Date: 2009-06-09
- Inventor: Feng Gao , Ya-Fen Lin , John W. Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
- Applicant: Feng Gao , Ya-Fen Lin , John W. Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
- Applicant Address: US CA Sunnyvale
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: DLA Piper LLP (US)
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.
Public/Granted literature
Information query
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