发明授权
US07553740B2 Structure and method for forming a minimum pitch trench-gate FET with heavy body region
失效
用于形成具有重体区域的最小间距沟槽栅FET的结构和方法
- 专利标题： Structure and method for forming a minimum pitch trench-gate FET with heavy body region
- 专利标题（中）： 用于形成具有重体区域的最小间距沟槽栅FET的结构和方法
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申请号： US11140567申请日： 2005-05-26
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公开(公告)号： US07553740B2公开(公告)日： 2009-06-30
- 发明人: Joelle Sharp , Gordon K. Madson
- 申请人： Joelle Sharp , Gordon K. Madson
- 申请人地址： US ME South Portland
- 专利权人： Fairchild Semiconductor Corporation
- 当前专利权人： Fairchild Semiconductor Corporation
- 当前专利权人地址： US ME South Portland
- 代理机构： Townsend and Townsend and Crew LLP
- 主分类号： H01L21/76
- IPC分类号： H01L21/76
摘要：
A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.
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