发明授权
US07565390B1 Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices
有权
用于促进在可编程逻辑器件中进行乘法累加操作的电路的电路
- 专利标题： Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices
- 专利标题（中）： 用于促进在可编程逻辑器件中进行乘法累加操作的电路的电路
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申请号： US11089684申请日： 2005-03-23
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公开(公告)号： US07565390B1公开(公告)日： 2009-07-21
- 发明人: Tat Mun Lui , Bee Yee Ng , Jun Pin Tan , Boon Jin Ang
- 申请人： Tat Mun Lui , Bee Yee Ng , Jun Pin Tan , Boon Jin Ang
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Ropes & Gray LLP
- 代理商 Robert R. Jackson
- 主分类号： G06F7/48
- IPC分类号： G06F7/48
摘要：
In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.
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