公开(公告)号：US08400863B1

公开(公告)日：2013-03-19

申请号：US12860734

申请日：2010-08-20

申请人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

发明人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

摘要翻译： 公开了用于存储器阵列的电路和操作可配置存储器块的方法。 所公开的存储器电路的实施例包括耦合到第二存储器块以形成存储器块阵列的第一存储器块。 每个存储器块具有多个位线，其中专用地址解码器耦合到来自每个存储器块的位线。 开关被放置在第一和第二存储器块之间，使得来自第一存储器块的每个位线通过其中一个开关连接到来自第二存储器块的相应位线。 交换机可以用于将第二存储器块连接到第一存储器块或将第二存储器块与第一存储器块断开。

公开(公告)号：US09680773B1

公开(公告)日：2017-06-13

申请号：US13245790

申请日：2011-09-26

申请人： Zun Yang Tan ,  Tat Mun Lui ,  Boon Jin Ang ,  Chiang Wei Lee ,  Richard Jin Guan Saw ,  Want Sent Khor

发明人： Zun Yang Tan ,  Tat Mun Lui ,  Boon Jin Ang ,  Chiang Wei Lee ,  Richard Jin Guan Saw ,  Want Sent Khor

IPC分类号： H04L12/861 ,  G06F5/12 ,  G06F1/32 ,  G11C5/14

CPC分类号： H04L49/9005 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3278 ,  G06F1/3287 ,  G06F5/12 ,  G11C5/148 ,  Y02D10/14 ,  Y02D10/157

摘要： One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.

公开(公告)号：US07683689B1

公开(公告)日：2010-03-23

申请号：US12082296

申请日：2008-04-10

申请人： Tat Mun Lui ,  Kar Keng Chua ,  Boon Jin Ang ,  Thow Pang Chong ,  Kam Fai Suit

发明人： Tat Mun Lui ,  Kar Keng Chua ,  Boon Jin Ang ,  Thow Pang Chong ,  Kam Fai Suit

IPC分类号： H03H11/26

CPC分类号： H03K5/133

摘要： A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.

摘要翻译： 描述了包括以第一取向取向的第一延迟单元和以第二取向定向的第二延迟单元的延迟电路。 在一个实施例中，第一取向垂直于第二取向。 更具体地，在一个实施例中，第一取向是垂直的，第二取向是水平的。

公开(公告)号：US07565390B1

公开(公告)日：2009-07-21

申请号：US11089684

申请日：2005-03-23

申请人： Tat Mun Lui ,  Bee Yee Ng ,  Jun Pin Tan ,  Boon Jin Ang

发明人： Tat Mun Lui ,  Bee Yee Ng ,  Jun Pin Tan ,  Boon Jin Ang

IPC分类号： G06F7/48

CPC分类号： G06F7/5443 ,  G06F7/4991 ,  H03K19/17704 ,  H03K19/17732

摘要： In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.

摘要翻译： 在诸如可编程逻辑器件（“PLD”）的电路中，几个乘法器块中的每一个包括部分乘积生成电路和部分乘积加法电路。 两个这样的乘法器块可以一起使用以提供乘法累加（“MAC”）能力。 一个配对块中的部分乘积加法电路用于将由另一个配对块产生的每个连续乘积加到先前提到的配对块中先前积累的乘积。 还提供了在第一提到的配对块中累积部分产品添加电路的操作的任何溢出的规定。