A method for operating a memory checker in a command monitoring architecture comprising at least two processing lanes comprises a first step of receiving a command to activate a first test mode. The first test mode comprises an initial step of inverting data read from a memory and inverting data written to the memory. Next, it is determined if there is a match between data associated with a first processing lane and retrieved by a second checker logic associated with a second processing lane and with data associated with a second processing lane and retrieved by a first checker logic associated with the first processing lane. A failure in the memory is determined if there is no match.