发明授权
- 专利标题: Verification of an extracted timing model file
- 专利标题(中): 提取的定时模型文件的验证
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申请号: US11376781申请日: 2006-03-15
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公开(公告)号: US07577928B2公开(公告)日: 2009-08-18
- 发明人: Peter Lindberg , Richard K. Kirchner , Sandeep Bhutani
- 申请人: Peter Lindberg , Richard K. Kirchner , Sandeep Bhutani
- 申请人地址: US CA Milpitas
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 当前专利权人地址: US CA Milpitas
- 代理机构: Ryan, Mason & Lewis, LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. An extracted timing model file is generated and a validation procedure is performed. This validation procedure may include comparing the information with the file to a test bench have a plurality of test points. In particular, data provided by the engineer is checked against multiple criteria to ensure that this data is valid and/or falls within an appropriate value range constraints. After the validation procedure has completed, the engineer is provided a summary of the validation results.
公开/授权文献
- US20070220462A1 Verification of an extracted timing model file 公开/授权日:2007-09-20
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