A method for manufacturing a plurality of memory devices and a plurality of high voltage devices on a substrate are provided. The substrate has a memory region and a high voltage region. The method comprises steps of forming a first dielectric layer on the substrate and then performing a thermal process so as to enlarge the thickness of the first dielectric layer in the high voltage region. A buried diffusion region is formed in the substrate in the memory region and a charge trapping layer and a blocking dielectric layer are formed over the substrate in the memory region. A patterned conductive layer is formed over the substrate so as to form gates the memory region and the high voltage region respectively and then a source/drain region is formed adjacent to the gates in the high voltage region in the substrate.