A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.