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    Programmable pin impedance reduction on multistandard input/outputs
    1.
    发明授权
    Programmable pin impedance reduction on multistandard input/outputs 有权
    多标准输入/输出可编程引脚阻抗降低

    公开(公告)号：US07239180B1

    公开(公告)日：2007-07-03

    申请号：US11135254

    申请日：2005-05-23

    申请人： Sergey Y Shumarayev

    发明人： Sergey Y Shumarayev

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/17744 ,  H03K19/1778

    摘要： Programmable logic devices, such as field programmable gate arrays, may have input/output (I/O) circuitry that can be programmed for either differential or single-ended signaling. I/O pins coupled to such programmable I/O circuitry typically have high parasitic input pin capacitance during differential signaling. I/O pins may also have high parasitic input pin inductance. Additional impedance circuit elements such as capacitive or inductive devices are coupled in the programmable I/O circuitry to produce a compensatory impedance that reduces, if not substantially eliminates, the effects of the parasitic input pin capacitance and/or inductance during differential signaling.

    摘要翻译： 诸如现场可编程门阵列之类的可编程逻辑器件可具有可编程为差分或单端信号的输入/输出（I / O）电路。 耦合到这种可编程I / O电路的I / O引脚在差分信号期间通常具有高寄生输入引脚电容。 I / O引脚也可能具有高寄生输入引脚电感。 额外的阻抗电路元件（例如电容或感应器件）耦合在可编程I / O电路中，以产生补偿阻抗，从而在差分信号传输期间减少（如果不是基本消除）寄生输入引脚电容和/或电感的影响。

    Integrated circuit delay chains
    2.
    发明授权
    Integrated circuit delay chains 有权
    集成电路延时链

    公开(公告)号：US07154324B1

    公开(公告)日：2006-12-26

    申请号：US10935867

    申请日：2004-09-07

    申请人： Simardeep Maangat ,  Sergey Y. Shumarayev

    发明人： Simardeep Maangat ,  Sergey Y. Shumarayev

    IPC分类号： H03H3/26

    CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/00058 ,  H03K2005/00143

    摘要： Delay chain circuitry is provided. The delay chain circuitry has a number of delay chain inverters. Each delay chain inverter is connected in series with a load resistor and has an associated capacitor between its input and ground. The electrodes of each capacitor may be formed from metal separated by non-gate-oxide dielectric to maintain accurate capacitor tolerances. A stable current source such as a bandgap reference current source may apply a current to a sensing resistor. The resulting bias voltage is indicative of changes in resistance due to changes in operating temperature. A temperature compensation circuit may use the bias voltage to produce temperature-compensation control signals. The temperature-compensation control signals are applied to the delay chain inverters to adjust their resistances and compensate for temperature-induced changes in the resistances of the load resistors. This ensures that the delay of the delay chain is independent of operating temperature.

    摘要翻译： 提供延迟链电路。 延迟链电路具有多个延迟链逆变器。 每个延迟链逆变器与负载电阻串联连接，并在其输入和地之间具有相关的电容器。 每个电容器的电极可以由由非栅极 - 氧化物电介质分离的金属形成，以保持精确的电容器公差。 诸如带隙参考电流源的稳定电流源可以向感测电阻器施加电流。 所产生的偏置电压表示由于工作温度变化引起的电阻变化。 温度补偿电路可以使用偏置电压来产生温度补偿控制信号。 温度补偿控制信号被施加到延迟链逆变器以调整其电阻并补偿负载电阻器的电阻的温度引起的变化。 这确保延迟链的延迟与工作温度无关。

    Integrated circuit devices with power supply detection circuitry
    3.
    发明授权
    Integrated circuit devices with power supply detection circuitry 失效

    公开(公告)号：US06985010B2

    公开(公告)日：2006-01-10

    申请号：US10753056

    申请日：2004-01-06

    申请人： Sergey Y. Shumarayev ,  Thomas H. White

    发明人： Sergey Y. Shumarayev ,  Thomas H. White

    IPC分类号： H03K19/003

    CPC分类号： H03K17/22 ,  G06F1/24 ,  G06F1/28

    摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

    Circuitry for providing programmable decision feedback equalization
    5.
    发明授权
    Circuitry for providing programmable decision feedback equalization 有权
    提供可编程判决反馈均衡的电路

    公开(公告)号：US07804892B1

    公开(公告)日：2010-09-28

    申请号：US11347527

    申请日：2006-02-03

    申请人： Sergey Y Shumarayev ,  Rakesh H Patel

    发明人： Sergey Y Shumarayev ,  Rakesh H Patel

    IPC分类号： H03H7/40

    CPC分类号： H04L25/03885 ,  H04L25/03057

    摘要： Equalization circuitry may be implemented by cascading a plurality of equalization stages. Each equalization stage may compensate for some of the attenuation of a received data signal. Each equalization stage may also be configured to perform decision feedback equalization to remove distortion from the current bit of data signal caused by one of the preceding bits in the data signal. Each equalization stage may be controlled by a DFE coefficient that determines the amount of voltage with which to adjust the output of the equalization stage. The equalization circuitry may be implemented on a receiver that includes clock data recovery circuitry and a pipeline/deserializer for providing preceding bit values to the equalization stages.

    摘要翻译： 均衡电路可以通过级联多个均衡级来实现。 每个均衡级可以补偿接收到的数据信号的一些衰减。 每个均衡级还可以被配置为执行判决反馈均衡以从数据信号中的前一位之一引起的数据信号的当前位中去除失真。 每个均衡级可以由DFE系数来控制，该DFE系数确定用于调整均衡级的输出的电压量。 均衡电路可以在包括时钟数据恢复电路和流水线/解串器的接收机上实现，用于向均衡级提供先前的位值。

    Programmable logic device architecture for accommodating specialized circuitry
    6.
    发明授权
    Programmable logic device architecture for accommodating specialized circuitry 失效
    用于容纳专用电路的可编程逻辑器件架构

    公开(公告)号：US07525340B2

    公开(公告)日：2009-04-28

    申请号：US11230002

    申请日：2005-09-19

    申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Chong H Lee

    发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Chong H Lee

    IPC分类号： G09F7/38 ,  H03K19/173 ,  H03K19/177 ,  H01L25/00

    CPC分类号： H03K19/17704 ,  H03K19/17732 ,  H03K19/17744

    摘要： A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the programmable logic device (and may be made on separate dies from the remainder of the programmable logic device mounted on a common substrate), and one or both of the programmable logic regions and the conventional I/O regions, have contacts for metallization traces or other interconnections to connect the peripheral specialized regions to the remainder of the programmable logic device. The same PLD can be sold with or without the specialized circuitry capability by providing or not providing the interconnections. The peripheral specialized regions may include high-speed I/O (basic, up to about 3 Gbps, and enhanced, up to about 10-12 Gbps), as well as other types of specialized circuitry.

    摘要翻译： 具有一个或多个可编程逻辑区域和一个或多个常规输入/输出区域的可编程逻辑器件（PLD）还具有包括专用电路的一个或多个外围区域。 外围专用区域不连接到可编程逻辑器件的其余部分（并且可以在与安装在公共衬底上的可编程逻辑器件的其余部分分开的管芯上）制造，以及一个或两个可编程逻辑区域 常规I / O区域具有用于金属化迹线或其它互连的触点，以将外围专用区域连接到可编程逻辑器件的其余部分。 通过提供或不提供互连，可以在具有或不具有专用电路能力的情况下出售相同的PLD。 外围专业区域可能包括高速I / O（基本，高达约3 Gbps，增强，高达10-12 Gbps）以及其他类型的专用电路。

    Programmable logic device multispeed I/O circuitry
    8.
    发明授权
    Programmable logic device multispeed I/O circuitry 有权
    可编程逻辑器件多速I / O电路

    公开(公告)号：US07135887B1

    公开(公告)日：2006-11-14

    申请号：US11013213

    申请日：2004-12-14

    申请人： Sergey Y. Shumarayev ,  Rakesh H. Patel

    发明人： Sergey Y. Shumarayev ,  Rakesh H. Patel

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K19/177

    摘要： Programmable logic device integrated circuitry having I/O circuitry portions having different maximum speed capabilities and different amounts of programmability for supporting various I/O signaling standards is provided. High-speed I/O circuitry and low-speed I/O circuitry may be provided. The high-speed I/O circuitry may have differential I/O drivers and may not be programmable. Relatively few I/O lines may be connected to the high-speed I/O circuitry. The low-speed I/O circuitry may be programmable so that a user may configure the low-speed I/O circuitry to support different I/O signaling standards. Intermediate-speed I/O circuitry may be provided that is more flexible than the high-speed circuitry and operates at higher maximum I/O data rates than the low-speed I/O circuitry. Transmitter circuitry (output driver circuitry) in the I/O circuitry may be provided with the ability to handle a greater number of different I/O signaling standards than receiver circuitry (input driver circuitry) in the I/O circuitry.

    摘要翻译： 提供了具有不同最大速度能力的I / O电路部分和用于支持各种I / O信令标准的不同数量的可编程性的可编程逻辑器件集成电路。 可以提供高速I / O电路和低速I / O电路。 高速I / O电路可能具有差分I / O驱动器，可能无法编程。 相对较少的I / O线可能连接到高速I / O电路。 低速I / O电路可以是可编程的，使得用户可以配置低速I / O电路以支持不同的I / O信令标准。 可以提供比高速电路更灵活的中速I / O电路，并且以比低速I / O电路更高的最大I / O数据速率工作。 I / O电路中的发射机电路（输出驱动器电路）可以具有处理比I / O电路中的接收机电路（输入驱动器电路）更多数量的不同I / O信令标准的能力。

    Integrated circuit output driver circuitry with programmable preemphasis
    9.
    发明授权
    Integrated circuit output driver circuitry with programmable preemphasis 有权
    具有可编程预加重功能的集成电路输出驱动器电路

    公开(公告)号：US07109743B2

    公开(公告)日：2006-09-19

    申请号：US11148046

    申请日：2005-06-07

    申请人： Sergey Y Shumarayev ,  Thomas H White ,  Rakesh H Patel ,  Wilson Wong

    发明人： Sergey Y Shumarayev ,  Thomas H White ,  Rakesh H Patel ,  Wilson Wong

    IPC分类号： H03K17/16

    CPC分类号： H03K19/17744 ,  H03K19/018585 ,  H03K19/1778 ,  H04L25/0272 ,  H04L25/0286

    摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

    摘要翻译： 提供了具有差分I / O电路的可编程逻辑器件集成电路。 差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。 用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。 用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

    Method and apparatus for multi-mode clock data recovery
    10.
    发明授权
    Method and apparatus for multi-mode clock data recovery 有权
    多模时钟数据恢复的方法和装置

    公开(公告)号：US08537954B2

    公开(公告)日：2013-09-17

    申请号：US12688617

    申请日：2010-01-15

    申请人： Sergey Y. Shumarayev ,  Rakesh H. Patel ,  Wilson Wong ,  Tim T. Hoang

    发明人： Sergey Y. Shumarayev ,  Rakesh H. Patel ,  Wilson Wong ,  Tim T. Hoang

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

    摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

    摘要翻译： 所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。 在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。 （CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。