发明授权
US07594212B1 Automatic pin placement for integrated circuits to aid circuit board design 有权
用于集成电路的自动引脚放置以辅助电路板设计

  • 专利标题: Automatic pin placement for integrated circuits to aid circuit board design
  • 专利标题(中): 用于集成电路的自动引脚放置以辅助电路板设计
  • 申请号: US11888162
    申请日: 2007-07-31
  • 公开(公告)号: US07594212B1
    公开(公告)日: 2009-09-22
  • 发明人: Dinesh D. GaitondeSalil Ravindra Raje
  • 申请人: Dinesh D. GaitondeSalil Ravindra Raje
  • 申请人地址: US CA San Jose
  • 专利权人: Xilinx, Inc.
  • 当前专利权人: Xilinx, Inc.
  • 当前专利权人地址: US CA San Jose
  • 代理商 Kevin T. Cuenot; Lois D. Cartier
  • 主分类号: G06F17/50
  • IPC分类号: G06F17/50
Automatic pin placement for integrated circuits to aid circuit board design
摘要:
A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for each of a plurality of banks of the IC, determining a cost of assigning the selected bus to the bank according, at least in part, to a measure of proximity of the bank to another bank including a bus of the interface. The method can include selecting an available bank having a lowest cost, assigning at least one of the plurality of I/O pins of the selected bus not assigned to a bank of the IC to the selected bank, and outputting a circuit design including an association of I/O pin(s) of the selected bus to the selected bank.
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