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1.发明申请CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN 有权从可编程逻辑器件电路设计创建标准单元电路设计公开(公告)号：US20090235222A1
公开(公告)日：2009-09-17
申请号：US12049676
申请日：2008-03-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist (110), mapping logic gates of the netlist to functionally equivalent standard cells (120), and including the standard cells within the standard cell circuit design (125). Design constraints for the standard cell circuit design can be automatically generated (135, 140). The design constraints for the standard cell circuit design can be output (145).
摘要翻译： 将可编程逻辑器件（PLD）的电路设计转换成标准单元电路设计的计算机实现的方法可以包括将PLD电路设计解映射到门级网表（110），将网表的逻辑门映射到功能等效的标准 单元（120），并且包括在标准单元电路设计（125）内的标准单元。 可以自动生成标准单元电路设计的设计约束（135,140）。 可以输出标准单元电路设计的设计约束（145）。
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公开(公告)号：US07519938B1
公开(公告)日：2009-04-14
申请号：US11543388
申请日：2006-10-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is provided for generating an implementation of an electronic design. Information describing a set of strategies is specified. Each strategy of the set includes one or more options for directing the generation of an implementation of the electronic design, with each option being a set of one or more input parameter values to an implementation tool. The set of strategies is displayed and a subset of the set of strategies is selected in response to user input. For each strategy of the subset, a respective implementation of the electronic design is generated from a specification of the electronic design in a hardware description language. The option or options of each strategy are input to one or more implementation tools to direct the generation of the respective implementation for the strategy. For each strategy of the subset, quality metrics are displayed for the respective implementation of the electronic design.
摘要翻译： 提供了一种用于产生电子设计的实现的方法。 指定描述一组策略的信息。 该集合的每个策略包括用于指导电子设计的实现的生成的一个或多个选项，其中每个选项是对实现工具的一个或多个输入参数值的集合。 显示该组策略，并且响应于用户输入选择策略集的一部分。 对于子集的每个策略，电子设计的相应实现是从硬件描述语言中的电子设计的规范生成的。 每个策略的选项或选项被输入到一个或多个实现工具中，以指导针对该策略的相应实现的生成。 对于子集的每个策略，显示电子设计的相应实现的质量度量。
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3.发明授权公开(公告)号：US07120892B1
公开(公告)日：2006-10-10
申请号：US10892613
申请日：2004-07-16
申请人： David A. Knol , Salil Ravindra Raje
发明人： David A. Knol , Salil Ravindra Raje
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock.
摘要翻译： 一种用于集成电路设计的地板计划工具，其为设计者提供工具和显示器，以通过创建由嵌套的pblock组成的物理层次来创建平面图，以定义在逻辑网表中定义的电路的期望位置。 每个pblock是一个数据结构，其中包含数据，该数据定义从逻辑网表分配哪些电路。 每个pblock都是独立的，可以输入到一个地方，而不需要物理层次结构的其余部分。 每个pblock数据结构包含指向该plbock的网表上的电路的指针，标识其中嵌套的其他pblock，并且至少包含该pblock的边界引脚列表。
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4.发明授权Data structures for representing the logical and physical information of an integrated circuit 有权用于表示集成电路的逻辑和物理信息的数据结构公开(公告)号：US07146595B2
公开(公告)日：2006-12-05
申请号：US10800042
申请日：2004-03-12
申请人： David A. Knol , Salil Ravindra Raje
发明人： David A. Knol , Salil Ravindra Raje
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock. Net data structures in the physical hierarchy define which nets are connected to which pins. PCellview data structures define the internal structure of each pblock.
摘要翻译： 一种用于集成电路设计的地板计划工具，其为设计者提供工具和显示器，以通过创建由嵌套的pblock组成的物理层次来创建平面图，以定义在逻辑网表中定义的电路的期望位置。 每个pblock是一个数据结构，其中包含数据，该数据定义从逻辑网表分配哪些电路。 每个pblock都是独立的，可以输入到一个地方，而不需要物理层次结构的其余部分。 每个pblock数据结构包含指向该plbock的网表上的电路的指针，标识其中嵌套的其他pblock，并且至少包含该pblock的边界引脚列表。 物理层次中的网络数据结构定义了哪些网络连接到哪些引脚。 PCellview数据结构定义每个pblock的内部结构。
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5.发明授权System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks 有权用于通过侵入逻辑块的逻辑层级而无限制地创建芯片的物理分层的系统公开(公告)号：US07117473B1
公开(公告)日：2006-10-03
申请号：US10892612
申请日：2004-07-16
申请人： David A. Knol , Salil Ravindra Raje
发明人： David A. Knol , Salil Ravindra Raje
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock.
摘要翻译： 一种用于集成电路设计的地板计划工具，其为设计者提供工具和显示器，以通过创建由嵌套的pblock组成的物理层次来创建平面图，以定义在逻辑网表中定义的电路的期望位置。 每个pblock是一个数据结构，其中包含数据，该数据定义从逻辑网表分配哪些电路。 每个pblock都是独立的，可以输入到一个地方，而不需要物理层次结构的其余部分。 每个pblock数据结构包含指向该plbock的网表上的电路的指针，标识其中嵌套的其他pblock，并且至少包含该pblock的边界引脚列表。
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6.发明授权System for representing the logical and physical information of an integrated circuit 有权用于表示集成电路的逻辑和物理信息的系统公开(公告)号：US07073149B2
公开(公告)日：2006-07-04
申请号：US10792164
申请日：2004-03-03
申请人： David A. Knol , Salil Ravindra Raje
发明人： David A. Knol , Salil Ravindra Raje
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested physical blocks (pblocks). Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that pblock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.
摘要翻译： 用于集成电路设计的地板计划工具，其为设计者提供工具和显示器，以通过创建由嵌套物理块（pblock）组成的物理层级来创建平面图，以定义逻辑网表中定义的电路的所需位置。 每个pblock是一个数据结构，其中包含数据，该数据定义从逻辑网表分配哪些电路。 每个pblock都是独立的，可以输入到一个地方，而不需要物理层次结构的其余部分。 每个pblock数据结构包含指向该pblock的网表上的电路的指针，标识嵌套在其中的其他pblock，并且包含pblock内的实例的引脚列表。 物理层次中的网络数据结构定义了哪些网络连接到哪些引脚。
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7.发明授权Creating a standard cell circuit design from a programmable logic device circuit design 有权从可编程逻辑器件电路设计创建标准单元电路设计公开(公告)号：US08667437B2
公开(公告)日：2014-03-04
申请号：US12049676
申请日：2008-03-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist, mapping logic gates of the netlist to functionally equivalent standard cells, and including the standard cells within the standard cell circuit design. Design constraints for the standard cell circuit design can be automatically generated. The design constraints for the standard cell circuit design can be output.
摘要翻译： 将可编程逻辑器件（PLD）的电路设计转换为标准单元电路设计的计算机实现的方法可以包括将PLD电路设计解映射到门级网表，将网表的逻辑门映射到功能等效的标准单元，以及 包括在标准单元电路设计中的标准单元。 可以自动生成标准单元电路设计的设计约束。 可以输出标准单元电路设计的设计约束。
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公开(公告)号：US07873927B1
公开(公告)日：2011-01-18
申请号：US12062447
申请日：2008-04-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality of instances can be from a different logic hierarchy. The method further can include automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances and creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.
摘要翻译： 跨多个集成电路划分设计的方法可以包括为多个集成电路中的每一个创建软件结构，并将多个实例分配给所选择的软件构造。 多个实例中的每一个可以来自不同的逻辑层级。 该方法还可以包括自动地将至少一个输入/输出缓冲器和端口添加到所选择的软件构造以容纳多个实例并且创建连接多个实例的网和所选择的软件中的至少一个输入/输出缓冲器和端口 构造。
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9.发明授权Automatic pin placement for integrated circuits to aid circuit board design 有权用于集成电路的自动引脚放置以辅助电路板设计公开(公告)号：US07594212B1
公开(公告)日：2009-09-22
申请号：US11888162
申请日：2007-07-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/40
摘要： A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for each of a plurality of banks of the IC, determining a cost of assigning the selected bus to the bank according, at least in part, to a measure of proximity of the bank to another bank including a bus of the interface. The method can include selecting an available bank having a lowest cost, assigning at least one of the plurality of I/O pins of the selected bus not assigned to a bank of the IC to the selected bank, and outputting a circuit design including an association of I/O pin(s) of the selected bus to the selected bank.
摘要翻译： 一种放置集成电路（IC）的电路设计的输入/输出（I / O）引脚的计算机实现方法可以包括从多个总线选择总线，其中所选择的总线包括多个I / O引脚 并且是接口的一部分，并且对于IC的多个银行中的每一个，确定至少部分地基于银行对另一银行的接近度的量度来将选择的总线分配给银行的成本，包括： 一个接口的总线。 该方法可以包括选择具有最低成本的可用存储体，将未被分配给IC组的所选择的总线的多个I / O引脚中的至少一个分配给所选择的存储体，并输出包括关联的电路设计 的所选总线的I / O引脚。
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10.发明授权System for representing the logical and physical information of an integrated circuit 有权用于表示集成电路的逻辑和物理信息的系统公开(公告)号：US07418686B1
公开(公告)日：2008-08-26
申请号：US11152502
申请日：2005-06-14
申请人： David A. Knol , Salil Ravindra Raje
发明人： David A. Knol , Salil Ravindra Raje
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.
摘要翻译： 一种用于集成电路设计的地板计划工具，其为设计者提供工具和显示器，以通过创建由嵌套的pblock组成的物理层次来创建平面图，以定义在逻辑网表中定义的电路的期望位置。 每个pblock是一个数据结构，其中包含数据，该数据定义从逻辑网表分配哪些电路。 每个pblock都是独立的，可以输入到一个地方，而不需要物理层次结构的其余部分。 每个pblock数据结构包含指向该plbock的网表上的电路的指针，标识嵌套在其中的其他pblock，并包含pblock中的实例的引脚列表。 物理层次中的网络数据结构定义了哪些网络连接到哪些引脚。
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