Invention Grant
- Patent Title: Wafer dicing method
- Patent Title (中): 晶圆切片方法
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Application No.: US11798503Application Date: 2007-05-14
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Publication No.: US07598157B2Publication Date: 2009-10-06
- Inventor: Chih-Hung Wu , Chieh Cheng , Kai-Sheng Chang , Kuan-Yu Chu
- Applicant: Chih-Hung Wu , Chieh Cheng , Kai-Sheng Chang , Kuan-Yu Chu
- Applicant Address: TW Taoyuan
- Assignee: Atomic Energy Countil-Institute of Nuclear Energy Research
- Current Assignee: Atomic Energy Countil-Institute of Nuclear Energy Research
- Current Assignee Address: TW Taoyuan
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A wafer stacked on a mounting layer is safely diced. The mounting layer has holes partially corresponding to chips on the wafer. Thus, chips obtained after dicing the wafer can be safely removed from the mounting tape. An amount of the mounting tape used can be reduced. And a production cost can be lowered as well.
Public/Granted literature
- US20080286946A1 Wafer dicing method Public/Granted day:2008-11-20
Information query
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