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发明授权
US07598540B2 High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same 有权
包括具有介质间隙填料的间隙双应激物的高性能CMOS器件及其制造方法

High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same
摘要：
The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.
摘要（中）：

本发明涉及具有间隙填充物的具有间隙双重应力的互补金属氧化物半导体（CMOS）器件。 具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。 拉伸应力介电层覆盖n-FET，并且压应力介电层覆盖p-FET。 间隙位于拉伸和压应力介电层之间，并填充有介电填料。 在本发明的一个具体实施方案中，拉伸和压缩应力介电层都被基本上没有应力的介电填料材料层覆盖。 在本发明的替代实施例中，电介质填充材料仅存在于拉伸和压缩应力介电层之间的间隙中。

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