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    High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same
    1.
    发明申请
    High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same 有权
    包括具有介质间隙填料的间隙双应激物的高性能CMOS器件及其制造方法

    公开(公告)号：US20070284617A1

    公开(公告)日：2007-12-13

    申请号：US11451869

    申请日：2006-06-13

    申请人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

    发明人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

    IPC分类号： H01L31/00 ,  H01L29/739

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

    摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

    摘要翻译： 本发明涉及具有间隙填充物的具有间隙双重应力的互补金属氧化物半导体（CMOS）器件。 具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。 拉伸应力介电层覆盖n-FET，并且压应力介电层覆盖p-FET。 间隙位于拉伸和压应力介电层之间，并填充有介电填料。 在本发明的一个具体实施方案中，拉伸和压缩应力介电层都被基本上没有应力的介电填料材料层覆盖。 在本发明的替代实施例中，电介质填充材料仅存在于拉伸和压缩应力介电层之间的间隙中。

    HIGH PERFORMANCE CMOS DEVICES COMPRISING GAPPED DUAL STRESSORS WITH DIELECTRIC GAP FILLERS, AND METHODS OF FABRICATING THE SAME
    2.
    发明申请
    HIGH PERFORMANCE CMOS DEVICES COMPRISING GAPPED DUAL STRESSORS WITH DIELECTRIC GAP FILLERS, AND METHODS OF FABRICATING THE SAME 有权
    包含带有电介质隙隙填料的双层压缩机的高性能CMOS器件及其制造方法

    公开(公告)号：US20090321847A1

    公开(公告)日：2009-12-31

    申请号：US12556261

    申请日：2009-09-09

    申请人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

    发明人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

    IPC分类号： H01L27/092 ,  H01L21/31 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

    摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

    摘要翻译： 本发明涉及具有间隙填充物的具有间隙双重应力的互补金属氧化物半导体（CMOS）器件。 具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。 拉伸应力介电层覆盖n-FET，并且压应力介电层覆盖p-FET。 间隙位于拉伸和压应力介电层之间，并填充有介电填料。 在本发明的一个具体实施方案中，拉伸和压缩应力介电层都被基本上没有应力的介电填料材料层覆盖。 在本发明的替代实施例中，电介质填充材料仅存在于拉伸和压缩应力介电层之间的间隙中。

    High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same
    3.
    发明授权
    High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same 有权
    包括具有介质间隙填料的间隙双应激物的高性能CMOS器件及其制造方法

    公开(公告)号：US07847357B2

    公开(公告)日：2010-12-07

    申请号：US12556261

    申请日：2009-09-09

    申请人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

    发明人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

    IPC分类号： H01L27/092 ,  H01L21/31 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

    摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

    摘要翻译： 本发明涉及具有间隙填充物的具有间隙双重应力的互补金属氧化物半导体（CMOS）器件。 具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。 拉伸应力介电层覆盖n-FET，并且压应力介电层覆盖p-FET。 间隙位于拉伸和压应力介电层之间，并填充有介电填料。 在本发明的一个具体实施方案中，拉伸和压缩应力介电层都被基本上没有应力的介电填料材料层覆盖。 在本发明的替代实施例中，电介质填充材料仅存在于拉伸和压缩应力介电层之间的间隙中。

    High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same
    4.
    发明授权
    High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same 有权
    包括具有介质间隙填料的间隙双应激物的高性能CMOS器件及其制造方法

    公开(公告)号：US07598540B2

    公开(公告)日：2009-10-06

    申请号：US11451869

    申请日：2006-06-13

    申请人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

    发明人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

    IPC分类号： H01L31/00 ,  H01L29/739

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

    摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

    摘要翻译： 本发明涉及具有间隙填充物的具有间隙双重应力的互补金属氧化物半导体（CMOS）器件。 具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。 拉伸应力介电层覆盖n-FET，并且压应力介电层覆盖p-FET。 间隙位于拉伸和压应力介电层之间，并填充有介电填料。 在本发明的一个具体实施方案中，拉伸和压缩应力介电层都被基本上没有应力的介电填料材料层覆盖。 在本发明的替代实施例中，电介质填充材料仅存在于拉伸和压缩应力介电层之间的间隙中。

    Highly scalable and distributed data sharing and storage
    5.
    发明授权
    Highly scalable and distributed data sharing and storage 有权
    高度可扩展和分布式数据共享和存储

    公开(公告)号：US08935431B2

    公开(公告)日：2015-01-13

    申请号：US12971129

    申请日：2010-12-17

    申请人： Sven Oehme ,  Marc Thadeus Roskow ,  Stephen Leonard Schwartz ,  Anna W. Topol ,  Daniel James Winarski

    发明人： Sven Oehme ,  Marc Thadeus Roskow ,  Stephen Leonard Schwartz ,  Anna W. Topol ,  Daniel James Winarski

    IPC分类号： G06F19/00 ,  G06F17/30

    CPC分类号： G06F17/30224 ,  G06F19/00 ,  G06F19/321

    摘要： Embodiments of the disclosure relate to storing and sharing data in a scalable distributed storing system using parallel file systems. An exemplary embodiment may comprise a network, a storage node coupled to the network for storing data, a plurality of application nodes in device and system modalities coupled to the network, and a parallel file structure disposed across the storage node and the application nodes to allow data storage, access and sharing through the parallel file structure. Other embodiments may comprise interface nodes for accessing data through various file access protocols, a storage management node for managing and archiving data, and a system management node for managing nodes in the system.

    摘要翻译： 本公开的实施例涉及使用并行文件系统在可扩展分布式存储系统中存储和共享数据。 示例性实施例可以包括网络，耦合到网络的用于存储数据的存储节点，耦合到网络的设备和系统模态中的多个应用节点以及跨过存储节点和应用节点设置的并行文件结构，以允许 数据存储，通过并行文件结构访问和共享。 其他实施例可以包括用于通过各种文件访问协议访问数据的接口节点，用于管理和归档数据的存储管理节点，以及用于管理系统中的节点的系统管理节点。

    METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR
    9.
    发明申请
    METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR 审中-公开
    形成晶体管和相关晶体管的方法

    公开(公告)号：US20100133616A1

    公开(公告)日：2010-06-03

    申请号：US12701685

    申请日：2010-02-08

    申请人： David J. Frank ,  Douglas C. La Tulipe, JR. ,  Steven E. Steen ,  Anna W. Topol

    发明人： David J. Frank ,  Douglas C. La Tulipe, JR. ,  Steven E. Steen ,  Anna W. Topol

    IPC分类号： H01L29/06

    CPC分类号： H01L29/66477 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.

    摘要翻译： 公开了向晶体管和相关晶体管布线的方法。 在一个实施例中，该方法包括一种向晶体管形成布线的方法，所述方法包括：使用作为预期布局的镜像的掩模在绝缘体上半导体（SOI）衬底上形成晶体管，所述形成包括形成 栅极和源极/漏极区域，所述SOI衬底包括绝缘体上半导体（SOI）层，掩埋绝缘体层和硅衬底; 在所述晶体管上形成介电层; 将介电层粘合到另一基底上; 将硅衬底从SOI衬底移除到掩埋绝缘体层; 从栅极的沟道侧形成与源极/漏极区域和栅极中的每一个的接触; 以及形成至少一条布线到栅极通道侧上的触点。

    Hermetic seal and reliable bonding structures for 3D applications
    10.
    发明授权
    Hermetic seal and reliable bonding structures for 3D applications 失效
    密封密封和3D应用的可靠结合结构

    公开(公告)号：US07683478B2

    公开(公告)日：2010-03-23

    申请号：US12026776

    申请日：2008-02-06

    申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

    发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

    IPC分类号： H01L23/34

    CPC分类号： H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

    摘要翻译： 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。