发明授权
US07601648B2 Method for fabricating an integrated gate dielectric layer for field effect transistors
有权
用于制造用于场效应晶体管的集成栅介质层的方法
- 专利标题： Method for fabricating an integrated gate dielectric layer for field effect transistors
- 专利标题（中）： 用于制造用于场效应晶体管的集成栅介质层的方法
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申请号： US11496411申请日： 2006-07-31
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公开(公告)号： US07601648B2公开(公告)日： 2009-10-13
- 发明人: Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
- 申请人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
- 申请人地址： US CA Santa Clara
- 专利权人： Applied Materials, Inc.
- 当前专利权人： Applied Materials, Inc.
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Patterson & Sheridan, LLP
- 主分类号： H01L21/31
- IPC分类号： H01L21/31
摘要：
Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.