发明授权
US07605042B2 SOI bottom pre-doping merged e-SiGe for poly height reduction
失效
SOI底部预掺杂合并的e-SiGe用于聚合高度减少
- 专利标题: SOI bottom pre-doping merged e-SiGe for poly height reduction
- 专利标题(中): SOI底部预掺杂合并的e-SiGe用于聚合高度减少
-
申请号: US11107843申请日: 2005-04-18
-
公开(公告)号: US07605042B2公开(公告)日: 2009-10-20
- 发明人: Yusuke Kohyama
- 申请人: Yusuke Kohyama
- 申请人地址: US CA Irvine
- 专利权人: Toshiba America Electronic Components, Inc.
- 当前专利权人: Toshiba America Electronic Components, Inc.
- 当前专利权人地址: US CA Irvine
- 代理机构: Banner & Witcoff, Ltd.
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor.
公开/授权文献
信息查询
IPC分类: