公开(公告)号：US20110250716A1

公开(公告)日：2011-10-13

申请号：US13166441

申请日：2011-06-22

Applicant: Yusuke KOHYAMA

Inventor： Yusuke KOHYAMA

IPC: H01L31/18

CPC classification number: H01L27/14689 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a solid-state image pick up device, a first conduction type semiconductor layer which has a first surface side. A second surface side which is located the opposite side of the first surface side and an image sensor area. A photo-conversion area which is configured in the first surface side and charges electron by photoelectric conversion. A first diffusion area of second conduction type for isolation, wherein the first diffusion area surrounds the photo-conversion area and extends from the first surface side to the middle part of the semiconductor layer and a second diffusion area of second conduction type for isolation, wherein the second diffusion area extends from the second surface side to the bottom of the first diffusion layer.

Abstract translation: 在固体摄像装置中，具有第一表面侧的第一导电型半导体层。 位于第一表面侧的相对侧的第二表面侧和图像传感器区域。 光转换区域，其配置在第一表面侧，并通过光电转换对电子进行充电。 用于隔离的第二导电类型的第一扩散区域，其中所述第一扩散区域围绕所述光转换区域并且从所述半导体层的第一表面侧延伸到所述中间部分，以及用于隔离的第二导电类型的第二扩散区域，其中 第二扩散区从第一扩散层的第二表面侧延伸到底部。

公开(公告)号：US20100006973A1

公开(公告)日：2010-01-14

申请号：US12402499

申请日：2009-03-12

Applicant: Yusuke KOHYAMA

Inventor： Yusuke KOHYAMA

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76251 ,  H01L21/76264

Abstract: A semiconductor device with STIs separating HOT regions is described. Processes for eliminating voids due to misalignments in boundary region STIs are described.

Abstract translation: 描述了具有分离HOT区域的STI的半导体器件。 描述了由于边界区域STI中的未对准而消除空隙的过程。

公开(公告)号：US20090315132A1

公开(公告)日：2009-12-24

申请号：US12486244

申请日：2009-06-17

Applicant: Yusuke KOHYAMA

Inventor： Yusuke KOHYAMA

IPC: H01L31/101 ,  H01L31/18

CPC classification number: H01L27/14689 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a solid-state image pick up device, a first conduction type semiconductor layer which has a first surface side. A second surface side which is located the opposite side of the first surface side and an image sensor area. A photo-conversion area which is configured in the first surface side and charges electron by photoelectric conversion. A first diffusion area of second conduction type for isolation, wherein the first diffusion area surrounds the photo-conversion area and extends from the first surface side to the middle part of the semiconductor layer and a second diffusion area of second conduction type for isolation, wherein the second diffusion area extends from the second surface side to the bottom of the first diffusion layer.

Abstract translation: 在固体摄像装置中，具有第一表面侧的第一导电型半导体层。 位于第一表面侧的相对侧的第二表面侧和图像传感器区域。 光转换区域，其配置在第一表面侧，并通过光电转换对电子进行充电。 用于隔离的第二导电类型的第一扩散区域，其中所述第一扩散区域围绕所述光转换区域并且从所述半导体层的第一表面侧延伸到所述中间部分，以及用于隔离的第二导电类型的第二扩散区域，其中 第二扩散区从第一扩散层的第二表面侧延伸到底部。

公开(公告)号：US07514752B2

公开(公告)日：2009-04-07

申请号：US11211604

申请日：2005-08-26

Applicant: Yusuke Kohyama

Inventor： Yusuke Kohyama

IPC: H01L29/76

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823871

Abstract: Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

Abstract translation: 描述了减少在拉伸和压缩衬里（T-C边界）之间的边界处的不同电位的触点之间发生意外的地铁短路的可能性。 这可以在不过度增加半导体器件的尺寸的情况下进行，或者甚至在以前的设计中增加尺寸。 例如，简单地通过调整装置的布局，两个不同公共栅极的触点可以相对于T-C边界相反的方向偏移。 或者，通过形成具有锯齿形或其他类似图案的T-C边界，可以将触点设置得更靠近在一起，同时仍然减少了地铁短路形成的可能性。 这样的布局调整不需要额外的步骤或成本。

公开(公告)号：US07163894B2

公开(公告)日：2007-01-16

申请号：US10927079

申请日：2004-08-27

Applicant: Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

Inventor： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC: H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

公开(公告)号：US20060124980A1

公开(公告)日：2006-06-15

申请号：US11333412

申请日：2006-01-18

Applicant: Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

Inventor： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC: H01L29/94

CPC classification number: H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

公开(公告)号：US06303429B1

公开(公告)日：2001-10-16

申请号：US09676084

申请日：2000-10-02

Applicant: Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

Inventor： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC: H01L218242

CPC classification number: H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

Abstract: Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

Abstract translation: 电容器形成在由氧化硅制成的层间绝缘体中制成的沟槽中。 绝缘膜（例如，氮化硅膜）设置在层间绝缘体的每个沟槽的侧面上。 在层间绝缘体的每个沟槽中设置由钌等制成的存储电极。 在存储电极上形成由BSTO等构成的电容绝缘膜。 在电容器绝缘膜上形成由钌等制成的平板电极。 平板电极对所有提供的电容器是共同的。 任何两个相邻的电容器通过层间绝缘体和设置在层间绝缘体的沟槽的侧面上的绝缘膜电隔离。

公开(公告)号：US06225230B1

公开(公告)日：2001-05-01

申请号：US08861736

申请日：1997-05-22

Applicant: Hiroyuki Nitta ,  Yusuke Kohyama

Inventor： Hiroyuki Nitta ,  Yusuke Kohyama

IPC: H01L2100

CPC classification number: H01L21/76229

Abstract: Disclosed is a method of forming an element isolation insulating film by STI (shallow trench isolation) method, which permits effectively preventing a concave portion from being formed in an edge of the element isolation insulating film, permits decreasing the number of treating steps, and also permits facilitating the formation of the element isolation insulating film with a high yield. In forming the element isolation insulating film, a groove is formed in a surface region of a semiconductor substrate, followed by forming an insulating film on the entire surface to fill at least the groove. Then, a flattening treatment is applied at least once to remove the insulating film from the substrate surface such that the insulating film is left unremoved only within the groove. In place of a wet etching treatment, a mirror-polishing method is employed for the last flattening treatment.

Abstract translation: 公开了通过STI（浅沟槽隔离）方法形成元件隔离绝缘膜的方法，其可有效地防止在元件隔离绝缘膜的边缘中形成凹部，从而减少处理步骤的数量，并且还 允许以高产率促进元件隔离绝缘膜的形成。 在形成元件隔离绝缘膜时，在半导体衬底的表面区域中形成沟槽，然后在整个表面上形成绝缘膜以至少填充沟槽。 然后，平坦化处理至少施加一次以从基板表面去除绝缘膜，使得绝缘膜仅在沟槽内不被移除。 代替湿蚀刻处理，最后的平坦化处理采用镜面抛光方法。

公开(公告)号：US06222722B1

公开(公告)日：2001-04-24

申请号：US09283280

申请日：1999-04-01

Applicant: Yoshiaki Fukuzumi ,  Yusuke Kohyama

Inventor： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC: H01G4008

CPC classification number: H01L28/82 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/86 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91

Abstract: This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an insulating interlayer having a contact plug. The capacitor has a lower electrode whose inner and outer surfaces are rough or undulated such that one surface has a shape conforming to the shape of the other surface, a dielectric film formed to cover the surfaces of the lower electrode, and an upper electrode formed to cover the lower electrode via the dielectric film. The lower electrode has a cylindrical shape with an open upper end. The lower electrode is connected to a cell transistor through the contact plug. The lower electrode is formed from a metal or a metal oxide.

公开(公告)号：US06198122B1

公开(公告)日：2001-03-06

申请号：US09025908

申请日：1998-02-19

Applicant: Mariko Habu ,  Yusuke Kohyama ,  Toru Ozaki ,  Keiji Hosotani

Inventor： Mariko Habu ,  Yusuke Kohyama ,  Toru Ozaki ,  Keiji Hosotani

IPC: H01L27108

CPC classification number: H01L27/10894 ,  H01L27/10852

Abstract: A semiconductor memory includes a semiconductor substrate, a memory cell portion formed on the substrate and including stacked capacitors formed on the substrate, each having a storage electrode formed on a bottom surface of a recess in an insulating layer, a capacitor insulating film formed on the storage electrode, and a plate electrode formed on the capacitor insulating film and lower than an upper edge of the recess, and a first multilayered interconnecting layer having an interconnecting layer including a plate interconnection connected to the plate electrode, and a peripheral circuit portion formed adjacent to the memory cell portion on the substrate and comprising a second multilayered interconnecting layer. The plate interconnection includes a portion so formed as to bury the recess and connected to the plate electrode, and the second multilayered interconnecting layer includes an interconnecting layer having an upper surface substantially leveled with an upper surface of the interconnecting layer including the plate interconnection of the first multilayered interconnecting layer.

Abstract translation: 半导体存储器包括半导体衬底，形成在衬底上的存储单元部分，并且包括形成在衬底上的叠层电容器，每个存储电极形成在绝缘层凹部的底表面上的存储电极，形成在绝缘层上的电容器绝缘膜 存储电极和形成在电容器绝缘膜上并低于凹部的上边缘的平板电极，以及具有互连层的第一多层互连层，所述互连层包括连接到平板电极的板状互连层，以及形成在邻接 到基板上的存储单元部分并且包括第二多层互连层。 板互连包括形成为埋入凹部并连接到平板电极的部分，并且第二多层互连层包括互连层，该互连层具有基本上与互连层的上表面大致平齐的互连层，包括互连层的板互连 第一多层互连层。