Invention Grant
- Patent Title: Method and system for wafer backside alignment
- Patent Title (中): 晶圆背面对准的方法和系统
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Application No.: US11409582Application Date: 2006-04-24
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Publication No.: US07611960B2Publication Date: 2009-11-03
- Inventor: Sheng-Chieh Liu , Chia-Hung Kao , Tzu-Yang Wu , Sheng-Liang Pan , Yuan-Bang Lee
- Applicant: Sheng-Chieh Liu , Chia-Hung Kao , Tzu-Yang Wu , Sheng-Liang Pan , Yuan-Bang Lee
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/302 ; H01L21/461
Abstract:
Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.
Public/Granted literature
- US20070249137A1 Method and system for wafer backside alignment Public/Granted day:2007-10-25
Information query
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