发明授权
US07619440B2 Circuit having logic state retention during power-down and method therefor
有权
断电期间具有逻辑状态保持的电路及其方法
- 专利标题： Circuit having logic state retention during power-down and method therefor
- 专利标题（中）： 断电期间具有逻辑状态保持的电路及其方法
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申请号： US12022199申请日： 2008-01-30
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公开(公告)号： US07619440B2公开(公告)日： 2009-11-17
- 发明人: Robert J. Amedeo , Christopher K. Y. Chun
- 申请人： Robert J. Amedeo , Christopher K. Y. Chun
- 申请人地址： US TX Austin
- 专利权人： Freescale Semiconductor, Inc.
- 当前专利权人： Freescale Semiconductor, Inc.
- 当前专利权人地址： US TX Austin
- 代理商 Daniel D. Hill; Robert L. King
- 主分类号： H03K17/16
- IPC分类号： H03K17/16 ; H03K19/003
摘要：
A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.
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