Techniques and circuits for ensuring one or more circuit components are not subjected to voltage levels above their rated voltage tolerance due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals used to program a voltage regulator. In response to determining the core logic voltage supply is below a predetermined level, the sense circuit may generate one or more regulated voltage signals to override regulated voltage signals generated by the voltage regulator.