A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.