公开(公告)号：US08724395B2

公开(公告)日：2014-05-13

申请号：US13483308

申请日：2012-05-30

申请人： Sang-Soo Park ,  Jae-Yong Jeong

发明人： Sang-Soo Park ,  Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3454

摘要： A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected memory cell. In each program loop, the nonvolatile memory device determines a program condition and increments the program voltage by an amount determined according to the program condition.

摘要翻译： 通过执行多个程序循环来编程非易失性存储器件，每个程序循环包括对所选择的字线施加编程电压以改变所选择的存储单元的阈值电压，以及将验证电压施加到所选择的字线以验证 选择的存储单元。 在每个程序循环中，非易失性存储器件确定程序状态，并使程序电压递增根据程序条件确定的量。

公开(公告)号：US20130135932A1

公开(公告)日：2013-05-30

申请号：US13618604

申请日：2012-09-14

申请人： Sang Hoon Lee ,  Hyun Seok Kim ,  Sung-Hwan Bae ,  Jong-Nam Baek ,  Jae Yong Jeong

发明人： Sang Hoon Lee ,  Hyun Seok Kim ,  Sung-Hwan Bae ,  Jong-Nam Baek ,  Jae Yong Jeong

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/26 ,  G11C29/00

摘要： A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.

公开(公告)号：US08214618B2

公开(公告)日：2012-07-03

申请号：US12216380

申请日：2008-07-02

申请人： Jae-yong Jeong

发明人： Jae-yong Jeong

IPC分类号： G06F12/00

CPC分类号： G06F12/10 ,  G06F11/203 ,  G06F12/0223

摘要： A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same memory access time when a task is migrated between processing cores by setting a memory allocation order according to distances from the processing cores to the memories in correspondence with the processing cores, translating a logical address to be processed by one of the processing cores according to the set memory allocation order into a physical address of one of the memories, and allocating a memory corresponding to the translated physical address to the processing core.

摘要翻译： 一种基于多核系统中的访问时间的存储器管理方法和装置。 在多核系统的存储器管理方法中，可以容易地估计由处理核心执行的任务的执行时间，并且当通过处理核心之间迁移任务时可以确保相同的存储器访问时间 根据与处理核心对应的从处理核心到存储器的距离设置存储器分配顺序，将要由处理核心之一处理的逻辑地址根据所设置的存储器分配顺序转换为处理核心之一的物理地址 存储器，并将与所翻译的物理地址相对应的存储器分配给处理核心。

公开(公告)号：US08045376B2

公开(公告)日：2011-10-25

申请号：US12615374

申请日：2009-11-10

申请人： Jung-Woo Lee ,  Jae-Yong Jeong

发明人： Jung-Woo Lee ,  Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C2211/5633

摘要： A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

摘要翻译： 一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字， 重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。

公开(公告)号：US07800944B2

公开(公告)日：2010-09-21

申请号：US12129820

申请日：2008-05-30

申请人： Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.

摘要翻译： 公开了一种非易失性存储器件的非易失性存储器件和编程方法。 非易失性存储器件的编程方法包括对存储器单元执行第一编程操作，在第一编程操作之后从存储单元检索原始数据，并参考原始数据和第二验证电压进行第二编程操作 比第一编程操作的第一验证电压。

公开(公告)号：US07599219B2

公开(公告)日：2009-10-06

申请号：US12031422

申请日：2008-02-14

申请人： Soo-Han Kim ,  Jae-Yong Jeong

发明人： Soo-Han Kim ,  Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/3454 ,  G11C16/3459

摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.

摘要翻译： 非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。 一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。 非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。 控制电路被配置为通过用具有第一级高度（例如，DeltaV1）的编程电压的第一阶梯级序列驱动阵列中的选定字线，然后响应于验证，执行多个存储器编程操作（P） 耦合到所选择的字线的存储单元中的至少一个是经过的存储单元，用具有低于第一台阶高度（例如，DeltaV2）的编程电压的第二阶梯顺序驱动所选择的字线 。

公开(公告)号：US20090193287A1

公开(公告)日：2009-07-30

申请号：US12216380

申请日：2008-07-02

申请人： Jae-yong Jeong

发明人： Jae-yong Jeong

IPC分类号： G06F12/02 ,  G06F11/20

CPC分类号： G06F12/10 ,  G06F11/203 ,  G06F12/0223

摘要： A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same memory access time when a task is migrated between processing cores by setting a memory allocation order according to distances from the processing cores to the memories in correspondence with the processing cores, translating a logical address to be processed by one of the processing cores according to the set memory allocation order into a physical address of one of the memories, and allocating a memory corresponding to the translated physical address to the processing core.

摘要翻译： 一种基于多核系统中的访问时间的存储器管理方法和装置。 在多核系统的存储器管理方法中，可以容易地估计由处理核心执行的任务的执行时间，并且当通过处理核心之间迁移任务时可以确保相同的存储器访问时间 根据与处理核心对应的从处理核心到存储器的距离设置存储器分配顺序，将要由处理核心之一处理的逻辑地址根据所设置的存储器分配顺序转换为处理核心之一的物理地址 存储器，并将与所翻译的物理地址相对应的存储器分配给处理核心。