发明授权
- 专利标题: Managing memory in a parallel processing environment
- 专利标题(中): 在并行处理环境中管理内存
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申请号: US11404187申请日: 2006-04-14
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公开(公告)号: US07624248B1公开(公告)日: 2009-11-24
- 发明人: David Wentzlaff , Anant Agarwal
- 申请人: David Wentzlaff , Anant Agarwal
- 申请人地址: US MA Westborough
- 专利权人: Tilera Corporation
- 当前专利权人: Tilera Corporation
- 当前专利权人地址: US MA Westborough
- 代理机构: Fish & Richardson P.C.
- 主分类号: G06F12/06
- IPC分类号: G06F12/06
摘要:
An integrated circuit comprises a plurality of tiles. Each tile comprises: a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled, and a translation lookaside buffer coupled to the switch to translate virtual memory addresses of switch instructions to physical memory addresses of the switch instructions.
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