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    Power switching semiconductor devices including rectifying junction-shunts
    4.
    发明授权
    Power switching semiconductor devices including rectifying junction-shunts 有权
    功率开关半导体器件包括整流结分路

    公开(公告)号：US08546874B2

    公开(公告)日：2013-10-01

    申请号：US13267966

    申请日：2011-10-07

    申请人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

    发明人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7803 ,  H01L21/0465 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/861

    摘要： A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.

    摘要翻译： 半导体器件包括漂移层和与漂移层形成p-n结的体区。 接触器区域在体区域中，并且分流通道区域从接触器区域延伸穿过体区域到漂移层。 分流沟道区域具有选择的长度，厚度和掺杂浓度，使得：1）当跨越第一和第二端子施加零电压时，并联沟道区域完全耗尽，2）并联沟道在小于 内部电位漂移层到体区pn结，和/或3）并联通道对于反向偏置漂移区域和体区之间的pn结的电压是不导通的。

    SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL
    7.
    发明申请
    SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL 有权
    具有高阻塞电压的SIC器件由负极水平端接

    公开(公告)号：US20120292636A1

    公开(公告)日：2012-11-22

    申请号：US13108366

    申请日：2011-05-16

    申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    IPC分类号： H01L29/161

    CPC分类号： H01L29/7813 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1004 ,  H01L29/1016 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/861

    摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

    摘要翻译： 公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。 在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。 更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。 在一个实施例中，期望的斜率小于或等于十五度。 在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。 半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET） 或PIN二极管。

    SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL
    8.
    发明申请
    SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL 有权
    具有高性能通道的半导体器件

    公开(公告)号：US20120223330A1

    公开(公告)日：2012-09-06

    申请号：US13039441

    申请日：2011-03-03

    申请人： Sarit Dhar ,  Sei-Hyung Ryu ,  Lin Cheng ,  Anant Agarwal

    发明人： Sarit Dhar ,  Sei-Hyung Ryu ,  Lin Cheng ,  Anant Agarwal

    IPC分类号： H01L29/161 ,  H01L21/22

    CPC分类号： H01L29/107 ,  H01L21/225 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/66568

    摘要： Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

    摘要翻译： 公开了具有高性能通道的半导体器件及其制造方法。 优选地，半导体器件是金属氧化物半导体（MOS）器件，并且甚至更优选半导体器件是碳化硅（SiC）MOS器件。 在一个实施例中，半导体器件包括第一导电类型的SiC衬底，第二导电类型的第一阱，第二导电类型的第二阱以及形成在第二导电类型的表面处的第二导电类型的表面扩散沟道 半导体器件在第一和第二阱之间。 控制表面扩散通道的深度和掺杂浓度，以便在处于导通状态同时保持导通状态或阈值时，与没有表面扩散沟道区的相同半导体器件相比，为半导体器件提供增加的载流子迁移率， 电压提供常态动作。

    Transistor with A-face conductive channel and trench protecting well region
    9.
    发明授权
    Transistor with A-face conductive channel and trench protecting well region 有权
    具有A面导电沟道和沟槽保护阱区的晶体管

    公开(公告)号：US08211770B2

    公开(公告)日：2012-07-03

    申请号：US13167806

    申请日：2011-06-24

    申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

    发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

    摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

    摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

    Memory access assignment for parallel processing architectures
    10.
    发明授权
    Memory access assignment for parallel processing architectures 有权
    并行处理架构的内存访问分配

    公开(公告)号：US08181168B1

    公开(公告)日：2012-05-15

    申请号：US12028007

    申请日：2008-02-07

    申请人： Walter Lee ,  Robert A. Gottlieb ,  Vineet Soni ,  Anant Agarwal ,  Richard Schooler

    发明人： Walter Lee ,  Robert A. Gottlieb ,  Vineet Soni ,  Anant Agarwal ,  Richard Schooler

    IPC分类号： G06F9/445

    CPC分类号： G06F8/41 ,  G06F8/445 ,  G06F12/0837

    摘要： A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; forming one or more memory analysis regions that include one or more of the subsets of instructions, where each subset of instructions is included in a single memory analysis region; analyzing each memory analysis region to partition memory objects and instructions that access the memory objects into equivalence classes such that instructions within an equivalence class only access objects in the same equivalence class; and assigning memory access instructions a given equivalence class to one of the computation units for execution on the assigned computation unit.

    摘要翻译： 一种系统包括由互连网互连的多个计算单元。 一种用于配置系统的方法包括形成与节目的不同部分相对应的指令子集，所述指令子集根据控制流程图相关; 形成包括指令子集中的一个或多个的一个或多个存储器分析区域，其中每个指令子集包括在单个存储器分析区域中; 分析每个存储器分析区域以将存储器对象和将存储器对象访问为等价类的指令分区，使得等价类中的指令仅访问相同等价类中的对象; 以及将存储器访问指令分配给给定的等价类别到所述计算单元之一，以便在所分配的计算单元上执行。