Invention Grant
US07629199B2 Method for fabricating semiconductor package with build-up layers formed on chip
有权
用于制造在芯片上形成积层的半导体封装的方法
- Patent Title: Method for fabricating semiconductor package with build-up layers formed on chip
- Patent Title (中): 用于制造在芯片上形成积层的半导体封装的方法
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Application No.: US11713362Application Date: 2007-03-01
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Publication No.: US07629199B2Publication Date: 2009-12-08
- Inventor: Chien-Ping Huang , Yu-Po Wang
- Applicant: Chien-Ping Huang , Yu-Po Wang
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW Taichung
- Agency: Edwards Angell Palmer & Dodge LLP
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW92113023A 20030514
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.
Public/Granted literature
- US20070158861A1 Method for fabricating semiconductor package with build-up layers formed on chip Public/Granted day:2007-07-12
Information query
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